Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy - HASP '13
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9781450321181

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Secure memories resistant to both random errors and fault injection attacks using nonlinear error correction codes

Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy - HASP '13 ◽

10.1145/2487726.2487731 ◽

2013 ◽

Cited By ~ 8

Author(s):

Shizun Ge ◽

Zhen Wang ◽

Pei Luo ◽

Mark Karpovsky

Keyword(s):

Error Correction ◽

Fault Injection ◽

Error Correction Codes ◽

Random Errors ◽

Nonlinear Error ◽

Injection Attacks ◽

Fault Injection Attacks

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Side-channel indistinguishability

Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy - HASP '13 ◽

10.1145/2487726.2487735 ◽

2013 ◽

Cited By ~ 16

Author(s):

Claude Carlet ◽

Sylvain Guilley

Keyword(s):

Side Channel

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Innovative instructions and software model for isolated execution

Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy - HASP '13 ◽

10.1145/2487726.2488368 ◽

2013 ◽

Cited By ~ 356

Author(s):

Frank McKeen ◽

Ilya Alexandrovich ◽

Alex Berenzon ◽

Carlos V. Rozas ◽

Hisham Shafi ◽

...

Keyword(s):

Software Model

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Evaluation of delay PUFs on CMOS 65 nm technology

Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy - HASP '13 ◽

10.1145/2487726.2487730 ◽

2013 ◽

Cited By ~ 4

Author(s):

Zouha Cherif ◽

Jean-Luc Danger ◽

Florent Lozac'h ◽

Yves Mathieu ◽

Lilian Bossuet

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Security testing of a secure cache design

Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy - HASP '13 ◽

10.1145/2487726.2487729 ◽

2013 ◽

Cited By ~ 16

Author(s):

Fangfei Liu ◽

Ruby B. Lee

Keyword(s):

Security Testing ◽

Cache Design

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Using innovative instructions to create trustworthy software solutions

Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy - HASP '13 ◽

10.1145/2487726.2488370 ◽

2013 ◽

Cited By ~ 148

Author(s):

Matthew Hoekstra ◽

Reshma Lal ◽

Pradeep Pappachan ◽

Vinay Phegade ◽

Juan Del Cuvillo

Keyword(s):

Trustworthy Software

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Side channel vulnerability metrics

Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy - HASP '13 ◽

10.1145/2487726.2487728 ◽

2013 ◽

Cited By ~ 16

Author(s):

Tianwei Zhang ◽

Fangfei Liu ◽

Si Chen ◽

Ruby B. Lee

Keyword(s):

Side Channel

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Practical template-algebraic side channel attacks with extremely low data complexity

Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy - HASP '13 ◽

10.1145/2487726.2487733 ◽

2013 ◽

Cited By ~ 7

Author(s):

Yossef Oren ◽

Ofir Weisse ◽

Avishai Wool

Keyword(s):

Side Channel ◽

Data Complexity ◽

Side Channel Attacks

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Micro-architectural support for metadata coherence in multi-core dynamic information flow tracking

Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy - HASP '13 ◽

10.1145/2487726.2487732 ◽

2013 ◽

Cited By ~ 1

Author(s):

Juan Carlos Martínez Santos ◽

Yunsi Fei

Keyword(s):

Information Flow ◽

Dynamic Information ◽

Architectural Support ◽

Information Flow Tracking ◽

Dynamic Information Flow Tracking

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Red team vs. blue team hardware trojan analysis

Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy - HASP '13 ◽

10.1145/2487726.2487727 ◽

2013 ◽

Cited By ~ 11

Author(s):

Michael Muehlberghuber ◽

Frank K. Gürkaynak ◽

Thomas Korak ◽

Philipp Dunst ◽

Michael Hutter

Keyword(s):

Hardware Trojan

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Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy - HASP '13Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

Secure memories resistant to both random errors and fault injection attacks using nonlinear error correction codes

Side-channel indistinguishability

Innovative instructions and software model for isolated execution

Evaluation of delay PUFs on CMOS 65 nm technology

Security testing of a secure cache design

Using innovative instructions to create trustworthy software solutions

Side channel vulnerability metrics

Practical template-algebraic side channel attacks with extremely low data complexity

Micro-architectural support for metadata coherence in multi-core dynamic information flow tracking

Red team vs. blue team hardware trojan analysis

Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy - HASP '13
Latest Publications