Signal Processing and Communications - Domain-Specific Processors
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Published By CRC Press

9780824747114, 9780203913185

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Automatic Synthesis Of Efficient Interfaces For Compiled Regular Architectures

Signal Processing and Communications - Domain-Specific Processors ◽

10.1201/9780203913185.ch7 ◽

2003 ◽

Cited By ~ 1

Author(s):

Anne-Claire Guillou ◽

Patrice Quinton ◽

Tanguy Risset ◽

Steven Derrien ◽

Charles Wagner

Keyword(s):

Automatic Synthesis

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Highly Efficient Scalable Parallel-Pipelined Architectures For Discrete Wavelet Transforms

Signal Processing and Communications - Domain-Specific Processors ◽

10.1201/9780203913185.ch3 ◽

2003 ◽

Author(s):

Aki Launiainen ◽

David Guevorkian ◽

Ville Lappalainen ◽

Petri Liuha

Keyword(s):

Wavelet Transforms ◽

Discrete Wavelet ◽

Discrete Wavelet Transforms ◽

Highly Efficient ◽

Pipelined Architectures ◽

Parallel Pipelined

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An Lut-Based High Level Synthesis Framework For Reconfigurable Architectures

Signal Processing and Communications - Domain-Specific Processors ◽

10.1201/9780203913185.ch2 ◽

2003 ◽

Cited By ~ 4

Author(s):

Lo√Øc Lagadec ◽

Oscar Villellas-Guillen ◽

Bernard Pottier

Keyword(s):

High Level Synthesis ◽

Reconfigurable Architectures ◽

High Level

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Signal Processing and Communications - Domain-Specific Processors ◽

10.1201/9780203913185.fmatt ◽

2003 ◽

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On Modeling Intra-Task Parallelism In Task-Level Parallel Embedded Systems

Signal Processing and Communications - Domain-Specific Processors ◽

10.1201/9780203913185.ch5 ◽

2003 ◽

Author(s):

Simon Polstra ◽

Joe Coffland ◽

Frank Terpstra ◽

Andy Pimentel

Keyword(s):

Embedded Systems ◽

Task Parallelism ◽

Task Level

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Stride Permutation Access In Interleaved Memory Systems

Signal Processing and Communications - Domain-Specific Processors ◽

10.1201/9780203913185.ch4 ◽

2003 ◽

Cited By ~ 5

Author(s):

Jarmo Takala ◽

Tuomas Ja√§rvinen

Keyword(s):

Memory Systems

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Goal-Driven Reconfiguration Of Polymorphous Architectures

Signal Processing and Communications - Domain-Specific Processors ◽

10.1201/9780203913185.ch8 ◽

2003 ◽

Author(s):

Sumit Lohani ◽

Shuvra Bhattacharyya

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Energy Estimation And Optimization For Piecewise Regular Processor Arrays

Signal Processing and Communications - Domain-Specific Processors ◽

10.1201/9780203913185.ch6 ◽

2003 ◽

Author(s):

Frank Hannig ◽

J√ºrgen Teich

Keyword(s):

Energy Estimation ◽

Processor Arrays

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Future Directions Of Programmable And Reconfigurable Embedded Processors

Signal Processing and Communications - Domain-Specific Processors ◽

10.1201/9780203913185.ch12 ◽

2003 ◽

Author(s):

Sorin Cotofana ◽

Stamatis Vassiliadis ◽

Stephan Wong

Keyword(s):

Embedded Processors ◽

Future Directions

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Single-Chip Multiprocessing For Consumer Electronics

Signal Processing and Communications - Domain-Specific Processors ◽

10.1201/9780203913185.ch11 ◽

2003 ◽

Cited By ~ 1

Author(s):

Paul Stravers ◽

Jan Hoogerbugge

Keyword(s):

Consumer Electronics ◽

Single Chip

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Signal Processing and Communications - Domain-Specific Processors
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By CRC Press

Automatic Synthesis Of Efficient Interfaces For Compiled Regular Architectures

Highly Efficient Scalable Parallel-Pipelined Architectures For Discrete Wavelet Transforms

An Lut-Based High Level Synthesis Framework For Reconfigurable Architectures

Contents

On Modeling Intra-Task Parallelism In Task-Level Parallel Embedded Systems

Stride Permutation Access In Interleaved Memory Systems

Goal-Driven Reconfiguration Of Polymorphous Architectures

Energy Estimation And Optimization For Piecewise Regular Processor Arrays

Future Directions Of Programmable And Reconfigurable Embedded Processors

Single-Chip Multiprocessing For Consumer Electronics

Export Citation Format

Signal Processing and Communications - Domain-Specific ProcessorsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By CRC Press

Automatic Synthesis Of Efficient Interfaces For Compiled Regular Architectures

Highly Efficient Scalable Parallel-Pipelined Architectures For Discrete Wavelet Transforms

An Lut-Based High Level Synthesis Framework For Reconfigurable Architectures

Contents

On Modeling Intra-Task Parallelism In Task-Level Parallel Embedded Systems

Stride Permutation Access In Interleaved Memory Systems

Goal-Driven Reconfiguration Of Polymorphous Architectures

Energy Estimation And Optimization For Piecewise Regular Processor Arrays

Future Directions Of Programmable And Reconfigurable Embedded Processors

Single-Chip Multiprocessing For Consumer Electronics

Signal Processing and Communications - Domain-Specific Processors
Latest Publications