1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)
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(FIVE YEARS 0)

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(FIVE YEARS 0)

Published By Japan Soc. Appl. Phys

4930813956

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Micro IDDQ test using Lorentz force MOSFETs

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) ◽

10.1109/vlsic.1999.797273 ◽

2003 ◽

Cited By ~ 2

Author(s):

K. Nose ◽

T. Sakurai

Keyword(s):

Lorentz Force

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A 1 V, 10.4 mW low power DSP core for mobile wireless use

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) ◽

10.1109/vlsic.1999.797218 ◽

2003 ◽

Cited By ~ 1

Author(s):

T. Shiota ◽

I. Fukushi ◽

R. Ohe ◽

W. Shibamoto ◽

M. Hamaminato ◽

...

Keyword(s):

Low Power ◽

Mobile Wireless

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A CMOS imager with new focal-plane motion detectors

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) ◽

10.1109/vlsic.1999.797264 ◽

2003 ◽

Cited By ~ 1

Author(s):

F. Okamoto ◽

Y. Fujimoto ◽

T. Nagata ◽

M. Furumiya ◽

K. Hatano ◽

...

Keyword(s):

Focal Plane ◽

Plane Motion ◽

Cmos Imager ◽

Motion Detectors

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A compact 54×54-bit multiplier with improved Wallace-tree structure

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) ◽

10.1109/vlsic.1999.797219 ◽

2003 ◽

Author(s):

N. Itoh ◽

Y. Naemura ◽

H. Makino ◽

Y. Nakase

Keyword(s):

Tree Structure ◽

Wallace Tree

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A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) ◽

10.1109/vlsic.1999.797217 ◽

2003 ◽

Cited By ~ 2

Author(s):

T. Xanthopoulos ◽

A. Chandrakasan

Keyword(s):

Low Power

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A 1 V 6 b 50 MHz current-interpolating CMOS ADC

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) ◽

10.1109/vlsic.1999.797242 ◽

2003 ◽

Author(s):

Bang-Sup Song ◽

Myung-Jun Choe ◽

P. Rakers ◽

S. Gillig

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A 1.0 ns access 770 MHz 36 Kb SRAM macro

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) ◽

10.1109/vlsic.1999.797253 ◽

2003 ◽

Cited By ~ 2

Author(s):

T. Uetake ◽

Y. Maki ◽

T. Nakadai ◽

K. Yoshida ◽

M. Susuki ◽

...

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Embedded DRAM for a reconfigurable array

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) ◽

10.1109/vlsic.1999.797266 ◽

2003 ◽

Cited By ~ 6

Author(s):

S. Perissakis ◽

Y. Joo ◽

J. Ahn ◽

A. Dellon ◽

J. Wawraynek

Keyword(s):

Reconfigurable Array

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A 1 Gbps transceiver with receiver-end deskewing capability using non-uniform tracked oversampling and a 250-750 MHz four-phase DLL

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) ◽

10.1109/vlsic.1999.797231 ◽

2003 ◽

Cited By ~ 1

Author(s):

Yongsam Moon ◽

Deog-Kyoon Jeong

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A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4 Gb DRAM's

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) ◽

10.1109/vlsic.1999.797259 ◽

2003 ◽

Author(s):

H. Hoenigschmid ◽

A. Frey ◽

J. DeBrosse ◽

T. Kirihata ◽

G. Mueller ◽

...

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1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Japan Soc. Appl. Phys

Micro IDDQ test using Lorentz force MOSFETs

A 1 V, 10.4 mW low power DSP core for mobile wireless use

A CMOS imager with new focal-plane motion detectors

A compact 54×54-bit multiplier with improved Wallace-tree structure

A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization

A 1 V 6 b 50 MHz current-interpolating CMOS ADC

A 1.0 ns access 770 MHz 36 Kb SRAM macro

Embedded DRAM for a reconfigurable array

A 1 Gbps transceiver with receiver-end deskewing capability using non-uniform tracked oversampling and a 250-750 MHz four-phase DLL

A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4 Gb DRAM's

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)
Latest Publications