Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9780769530987, 0769530982

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Invited Talk 2 - Optical Interconnects for Backplane and Chip-to-Chip Photonics

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008) ◽

10.1109/nocs.2008.4492719 ◽

2008 ◽

Author(s):

Ian H White ◽

Richard V. Penty

Keyword(s):

Optical Interconnects

Download Full-text

Circuit-Switched Coherence

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008) ◽

10.1109/nocs.2008.4492738 ◽

2008 ◽

Cited By ~ 48

Author(s):

Natalie D. Enright Jerger ◽

Li-Shiuan Peh ◽

Mikko H. Lipasti

Download Full-text

Statistical Approach to NoC Design

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008) ◽

10.1109/nocs.2008.4492736 ◽

2008 ◽

Cited By ~ 2

Author(s):

Itamar Cohen ◽

Ori Rottenstreich ◽

Isaac Keslassy

Keyword(s):

Statistical Approach

Download Full-text

Network Simplicity for Latency Insensitive Cores

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008) ◽

10.1109/nocs.2008.4492741 ◽

2008 ◽

Cited By ~ 1

Author(s):

Daniel Gebhardt ◽

JunBok You ◽

W. Scott Lee ◽

Kenneth S. Stevens

Keyword(s):

Latency Insensitive

Download Full-text

Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008) ◽

10.1109/nocs.2008.4492729 ◽

2008 ◽

Cited By ~ 14

Author(s):

Maurizio Palesi ◽

Giuseppe Longo ◽

Salvatore Signorino ◽

Rickard Holsmark ◽

Shashi Kumar ◽

...

Keyword(s):

Routing Algorithms ◽

Networks On Chip ◽

On Chip

Download Full-text

An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008) ◽

10.1109/nocs.2008.4492744 ◽

2008 ◽

Cited By ~ 12

Author(s):

Luis A. Plana ◽

John Bainbridge ◽

Steve Furber ◽

Sean Salisbury ◽

Yebin Shi ◽

...

Keyword(s):

Massively Parallel ◽

Neural Net ◽

Communications Network ◽

On Chip

Download Full-text

Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008) ◽

10.1109/nocs.2008.4492735 ◽

2008 ◽

Cited By ~ 103

Author(s):

Zheng Shi ◽

Alan Burns

Keyword(s):

Real Time ◽

Communication Analysis ◽

Wormhole Switching ◽

On Chip

Download Full-text

Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008) ◽

10.1109/nocs.2008.4492739 ◽

2008 ◽

Cited By ~ 8

Author(s):

S. Suboh ◽

M. Bakhouya ◽

T. El-Ghazawi

Keyword(s):

Interconnect Architectures ◽

On Chip ◽

Simulation And Evaluation

Download Full-text

Invited Talk 1- Past, Present, and Future Communicating Processors

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008) ◽

10.1109/nocs.2008.4492718 ◽

2008 ◽

Author(s):

David May

Download Full-text

ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008) ◽

10.1109/nocs.2008.4492725 ◽

2008 ◽

Cited By ~ 86

Author(s):

Mikkel Bystrup Stensgaard ◽

Jens Spars

Keyword(s):

Network On Chip ◽

On Chip

Download Full-text

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Invited Talk 2 - Optical Interconnects for Backplane and Chip-to-Chip Photonics

Circuit-Switched Coherence

Statistical Approach to NoC Design

Network Simplicity for Latency Insensitive Cores

Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms

An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator

Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching

Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network

Invited Talk 1- Past, Present, and Future Communicating Processors

ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)
Latest Publications