Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing
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A fast test to generate flash memory threshold voltage distribution map

Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1999.782687 ◽

2003 ◽

Cited By ~ 1

Author(s):

R. Khubchandani

Keyword(s):

Threshold Voltage ◽

Flash Memory ◽

Distribution Map ◽

Voltage Distribution ◽

Threshold Voltage Distribution

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Low-power SRAM circuit design

Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1999.782692 ◽

2003 ◽

Cited By ~ 24

Author(s):

M. Margala

Keyword(s):

Low Power ◽

Circuit Design

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Unbalanced cache systems

Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1999.782679 ◽

2003 ◽

Author(s):

D.L. Rhodes ◽

W. Wolf

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Design validation of .18 μm 1 GHz cache and register arrays

Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1999.782684 ◽

2003 ◽

Author(s):

D. Malone

Keyword(s):

Design Validation

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The dynamic associative access memory chip and its application to SIMD processing and full-text database retrieval

Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1999.782680 ◽

2003 ◽

Cited By ~ 3

Author(s):

G.J. Lipovski ◽

C. Yu

Keyword(s):

Full Text ◽

Access Memory ◽

Memory Chip ◽

Database Retrieval ◽

Simd Processing ◽

Text Database

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A comparative simulation study of four multilevel DRAMs

Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1999.782690 ◽

2003 ◽

Cited By ~ 9

Author(s):

G. Birk ◽

D.G. Elliott ◽

B.F. Cockburn

Keyword(s):

Simulation Study

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Tutorial: characterizing SDRAMs

Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1999.782685 ◽

2003 ◽

Cited By ~ 2

Author(s):

J. Voilrath

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Designing a memory module tester

Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1999.782689 ◽

2003 ◽

Author(s):

D.P. van der Velde ◽

A.J. v.d. Goor

Keyword(s):

Memory Module

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Built in self test for ring addressed FIFOs with transparent latches

Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1999.782686 ◽

2003 ◽

Author(s):

L. Fenstermaker ◽

Ilyoung Kim ◽

J. Lewandowski ◽

J.J. Nagy

Keyword(s):

Self Test ◽

Built In Self Test

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Determining redundancy requirements for memory arrays with critical area analysis

Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1999.782683 ◽

2003 ◽

Cited By ~ 16

Author(s):

J.D. Segal ◽

S. Bakarian ◽

J.E. Colburn ◽

M. Kumar ◽

C. Hong ◽

...

Keyword(s):

Critical Area ◽

Memory Arrays

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Records of the 1999 IEEE International Workshop on Memory Technology, Design and TestingLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A fast test to generate flash memory threshold voltage distribution map

Low-power SRAM circuit design

Unbalanced cache systems

Design validation of .18 μm 1 GHz cache and register arrays

The dynamic associative access memory chip and its application to SIMD processing and full-text database retrieval

A comparative simulation study of four multilevel DRAMs

Tutorial: characterizing SDRAMs

Designing a memory module tester

Built in self test for ring addressed FIFOs with transparent latches

Determining redundancy requirements for memory arrays with critical area analysis

Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing
Latest Publications