Proceedings. 1995 IEEE International Verilog HDL Conference
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Published By IEEE

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Alis: a light-weight logic synthesis for digital signal processing of audio visual

Proceedings. 1995 IEEE International Verilog HDL Conference ◽

10.1109/ivc.1995.512466 ◽

2002 ◽

Author(s):

T. Yatani ◽

K. Sato ◽

M. Niizato

Keyword(s):

Signal Processing ◽

Digital Signal Processing ◽

Logic Synthesis ◽

Digital Signal ◽

Light Weight

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Verilog modeling and simulation of a communication coprocessor for multicomputers

Proceedings. 1995 IEEE International Verilog HDL Conference ◽

10.1109/ivc.1995.512469 ◽

2002 ◽

Cited By ~ 1

Author(s):

A. Shyamprakash ◽

C.P. Ravikumar

Keyword(s):

Modeling And Simulation

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Writing style for architectural synthesis

Proceedings. 1995 IEEE International Verilog HDL Conference ◽

10.1109/ivc.1995.512504 ◽

2002 ◽

Cited By ~ 1

Author(s):

D.R. Smith

Keyword(s):

Writing Style ◽

Architectural Synthesis

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Measuring HDL-based design productivity: an experimental comparison

Proceedings. 1995 IEEE International Verilog HDL Conference ◽

10.1109/ivc.1995.512467 ◽

2002 ◽

Cited By ~ 2

Author(s):

M. Joshi ◽

H. Kim ◽

H. Kobayashi

Keyword(s):

Experimental Comparison

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A virtual memory management scheme for simulation environment

Proceedings. 1995 IEEE International Verilog HDL Conference ◽

10.1109/ivc.1995.512505 ◽

2002 ◽

Author(s):

S. Mittra

Keyword(s):

Memory Management ◽

Virtual Memory ◽

Simulation Environment ◽

Virtual Memory Management ◽

Management Scheme

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Incrementally recompiling Verilog

Proceedings. 1995 IEEE International Verilog HDL Conference ◽

10.1109/ivc.1995.512507 ◽

2002 ◽

Author(s):

Chong Guan Tan

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A comprehensive pre-RTL IC design methodology

Proceedings. 1995 IEEE International Verilog HDL Conference ◽

10.1109/ivc.1995.512506 ◽

2002 ◽

Cited By ~ 1

Author(s):

P.P. Jain

Keyword(s):

Design Methodology ◽

Ic Design

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An integrated environment for HDL verification

Proceedings. 1995 IEEE International Verilog HDL Conference ◽

10.1109/ivc.1995.512463 ◽

2002 ◽

Cited By ~ 7

Author(s):

G. York ◽

R. Mueller-Thuns ◽

J. Patel ◽

D. Beatty

Keyword(s):

Integrated Environment

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Cycle simulation techniques

Proceedings. 1995 IEEE International Verilog HDL Conference ◽

10.1109/ivc.1995.512462 ◽

2002 ◽

Cited By ~ 5

Author(s):

S. Palnitkar ◽

D. Parham

Keyword(s):

Simulation Techniques ◽

Cycle Simulation

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Standardizing delay calculation in Verilog

Proceedings. 1995 IEEE International Verilog HDL Conference ◽

10.1109/ivc.1995.512468 ◽

2002 ◽

Author(s):

K. Siomalas

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Proceedings. 1995 IEEE International Verilog HDL ConferenceLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Alis: a light-weight logic synthesis for digital signal processing of audio visual

Verilog modeling and simulation of a communication coprocessor for multicomputers

Writing style for architectural synthesis

Measuring HDL-based design productivity: an experimental comparison

A virtual memory management scheme for simulation environment

Incrementally recompiling Verilog

A comprehensive pre-RTL IC design methodology

An integrated environment for HDL verification

Cycle simulation techniques

Standardizing delay calculation in Verilog

Proceedings. 1995 IEEE International Verilog HDL Conference
Latest Publications