Defect and Fault Tolerance in VLSI Systems
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Published By Springer US

9781475799590, 9781475799576

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ASP Modules: WSI Building-Blocks for Cost-Effective Parallel Computing

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4757-9957-6_8 ◽

1990 ◽

pp. 99-109

Author(s):

R. M. Lea

Keyword(s):

Parallel Computing ◽

Cost Effective ◽

Building Blocks

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A Unified Approach to Yield Analysis of Defect Tolerant Circuits

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4757-9957-6_3 ◽

1990 ◽

pp. 33-45 ◽

Cited By ~ 8

Author(s):

Z. Koren ◽

I. Koren

Keyword(s):

Unified Approach ◽

Yield Analysis

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A Hyhpercube Design on WSI

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4757-9957-6_23 ◽

1990 ◽

pp. 283-294

Author(s):

H. Ito ◽

N. Suzuki

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A Fault Detection and Tolerance Tradeoff Evaluation Methodology for VLSI Systems

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4757-9957-6_22 ◽

1990 ◽

pp. 267-281 ◽

Cited By ~ 1

Author(s):

D. L. Landis ◽

J. R. Samson ◽

J. H. Aldridge

Keyword(s):

Fault Detection ◽

Evaluation Methodology

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SRAM/TEG Yield Methodology

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4757-9957-6_21 ◽

1990 ◽

pp. 253-266 ◽

Cited By ~ 2

Author(s):

H. G. Parks

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Yield Models - Comparative Study

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4757-9957-6_2 ◽

1990 ◽

pp. 15-31 ◽

Cited By ~ 6

Author(s):

W. Maly

Keyword(s):

Comparative Study

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Fault Tolerance in Analog VLSI: Case Study of a Focal Plane Processor

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4757-9957-6_19 ◽

1990 ◽

pp. 227-240 ◽

Cited By ~ 5

Author(s):

A. G. Andreou ◽

S. A. Kontogiorgis

Keyword(s):

Fault Tolerance ◽

Focal Plane ◽

Analog Vlsi

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APES: An Evaluation Environment of Fault-Tolerance Capabilities of Array Processors

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4757-9957-6_12 ◽

1990 ◽

pp. 149-159

Author(s):

F. Distante ◽

V. Piuri

Keyword(s):

Fault Tolerance ◽

Array Processors

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Fault-Tolerant k-out-of-n Logic Unit Network with Minimum Interconnection

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4757-9957-6_9 ◽

1990 ◽

pp. 111-122 ◽

Cited By ~ 3

Author(s):

E. Fujiwara

Keyword(s):

Fault Tolerant ◽

Unit Network ◽

Logic Unit

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Systematic Extraction of Critical Areas From IC Layouts

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4757-9957-6_4 ◽

1990 ◽

pp. 47-61 ◽

Cited By ~ 3

Author(s):

J. Pineda de Gyvez ◽

J. A. G. Jess

Keyword(s):

Critical Areas

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