Defect and Fault Tolerance in VLSI Systems
Latest Publications

TOTAL DOCUMENTS

31

(FIVE YEARS 0)

H-INDEX

7

(FIVE YEARS 0)

Published By Springer US

9781461568018, 9781461567998

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Design of a Fault-Tolerant DRAM with New On-Chip ECC

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4615-6799-8_8 ◽

1989 ◽

pp. 85-92 ◽

Cited By ~ 4

Author(s):

P. Mazumder

Keyword(s):

Fault Tolerant ◽

On Chip

Download Full-text

Defects, Faults and Semiconductor Device Yield

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4615-6799-8_3 ◽

1989 ◽

pp. 33-46 ◽

Cited By ~ 8

Author(s):

A. V. Ferris-Prabhu

Keyword(s):

Semiconductor Device

Download Full-text

Probabilistic Analysis of Yield and Area Utilization of Reconfigurable Rectangular Processor Arrays

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4615-6799-8_24 ◽

1989 ◽

pp. 269-280 ◽

Cited By ~ 9

Author(s):

Ajai Jain ◽

Janusz Rajski

Keyword(s):

Probabilistic Analysis ◽

Processor Arrays

Download Full-text

Measurement and Distribution of Faults on Defect Test Site Chips

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4615-6799-8_9 ◽

1989 ◽

pp. 93-104 ◽

Cited By ~ 7

Author(s):

Reinhard Glang

Keyword(s):

Test Site

Download Full-text

Defect Tolerant Interconnects for VLSI

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4615-6799-8_6 ◽

1989 ◽

pp. 65-76 ◽

Cited By ~ 3

Author(s):

Michael C. Howells ◽

Robert Aitken ◽

Vinod K. Agarwal

Download Full-text

A New Yield Formula for Fault-Tolerant Large-Area Devices

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4615-6799-8_5 ◽

1989 ◽

pp. 53-64 ◽

Cited By ~ 8

Author(s):

C. Thibeault ◽

Y. Savaria ◽

J.-L. Houle

Keyword(s):

Fault Tolerant ◽

Large Area ◽

Yield Formula

Download Full-text

On the Probability of Fault Occurrence

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4615-6799-8_4 ◽

1989 ◽

pp. 47-52 ◽

Cited By ~ 15

Author(s):

Sharad C. Seth ◽

Vishwani D. Agrawal

Download Full-text

On the Analysis and Design of Hierarchical Fault-Tolerant Processor Arrays

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4615-6799-8_31 ◽

1989 ◽

pp. 347-355 ◽

Cited By ~ 1

Author(s):

Y-X. Wang ◽

Jose A. B. Fortes

Keyword(s):

Fault Tolerant ◽

Analysis And Design ◽

Processor Arrays

Download Full-text

Block Alignment: A Method for Increasing the Yield of Memory Chips That are Partially Good

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4615-6799-8_22 ◽

1989 ◽

pp. 243-255 ◽

Cited By ~ 16

Author(s):

C. H. Stapper

Download Full-text

Defect Tolerance in a 16-Bit Microprocessor

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4615-6799-8_17 ◽

1989 ◽

pp. 179-190 ◽

Cited By ~ 6

Author(s):

Regis Leveugle ◽

Mohammad Soueidan ◽

Norbert Wehn

Keyword(s):

Defect Tolerance

Download Full-text