Proceedings of International Workshop on Defect and Fault Tolerance in VLSI
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0818671076

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI ◽

10.1109/dftvs.1995.476932 ◽

2002 ◽

Cited By ~ 9

Author(s):

I. Bubel ◽

W. Maly ◽

T. Waas ◽

P.K. Nag ◽

H. Hartmann ◽

...

Keyword(s):

Critical Area

Download Full-text

Characterization and analysis of errors in circuit test

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI ◽

10.1109/dftvs.1995.476960 ◽

2002 ◽

Cited By ~ 1

Author(s):

T. Ziaja ◽

E. Swartzlander

Download Full-text

FFT-based test of a yield monitor circuit

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI ◽

10.1109/dftvs.1995.476958 ◽

2002 ◽

Author(s):

C. Thibeault ◽

A. Payeur

Keyword(s):

Yield Monitor

Download Full-text

Efficient time redundancy for error correcting inner-product units and convolvers

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI ◽

10.1109/dftvs.1995.476953 ◽

2002 ◽

Author(s):

Yuang-Ming Hsu ◽

V. Piuri ◽

E.E. Swartzlander

Keyword(s):

Inner Product ◽

Time Redundancy

Download Full-text

A model for the evaluation of fault tolerance in the FERMI system

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI ◽

10.1109/dftvs.1995.476939 ◽

2002 ◽

Cited By ~ 1

Author(s):

A. Antola ◽

L. Breveglieri

Keyword(s):

Fault Tolerance ◽

Fermi System

Download Full-text

Design of defect-tolerant scan chains for MCMs with an active substrate

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI ◽

10.1109/dftvs.1995.476959 ◽

2002 ◽

Cited By ~ 1

Author(s):

P. Brahic ◽

R. Leveugle ◽

G. Saucier

Keyword(s):

Active Substrate ◽

Scan Chains

Download Full-text

Totally defect-tolerant arrays capable of quick broadcasting

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI ◽

10.1109/dftvs.1995.476944 ◽

2002 ◽

Cited By ~ 6

Author(s):

N. Tsuda ◽

T. Ishikawa ◽

Y. Nakamura

Download Full-text

Utilizing spares in multichip modules for the dual function of fault coverage and fault diagnosis

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI ◽

10.1109/dftvs.1995.476957 ◽

2002 ◽

Cited By ~ 5

Author(s):

S. Goldberg ◽

S.J. Upadhyaya

Keyword(s):

Fault Diagnosis ◽

Fault Coverage ◽

Dual Function ◽

Multichip Modules

Download Full-text

Accurate yield estimation of circuits with redundancy

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI ◽

10.1109/dftvs.1995.476948 ◽

2002 ◽

Cited By ~ 2

Author(s):

D.D. Gaitonde ◽

D.M.H. Walker ◽

W. Maly

Keyword(s):

Yield Estimation

Download Full-text

Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI ◽

10.1109/dftvs.1995.476940 ◽

2002 ◽

Cited By ~ 4

Author(s):

R. Narasimhan ◽

D.J. Rosenkrantz ◽

S.S. Ravi

Keyword(s):

Fault Tolerant ◽

Efficient Algorithms

Download Full-text

Proceedings of International Workshop on Defect and Fault Tolerance in VLSILatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout

Characterization and analysis of errors in circuit test

FFT-based test of a yield monitor circuit

Efficient time redundancy for error correcting inner-product units and convolvers

A model for the evaluation of fault tolerance in the FERMI system

Design of defect-tolerant scan chains for MCMs with an active substrate

Totally defect-tolerant arrays capable of quick broadcasting

Utilizing spares in multichip modules for the dual function of fault coverage and fault diagnosis

Accurate yield estimation of circuits with redundancy

Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI
Latest Publications