International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
Latest Publications

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Published By IEEE Comput. Soc

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Power and performance fitting in nanometer design

International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2002.1035012 ◽

2003 ◽

Cited By ~ 1

Author(s):

T. Sato ◽

T. Koushiro ◽

A. Chiyonobu ◽

I. Arita

Keyword(s):

And Performance ◽

Fitting In

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Architecture and compiler co-optimization for high performance computing

International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2002.1035018 ◽

2003 ◽

Cited By ~ 2

Author(s):

H. Nakamura ◽

M. Kondo ◽

T. Ohneda ◽

M. Fujita ◽

S. Chiba ◽

...

Keyword(s):

High Performance Computing ◽

High Performance ◽

Performance Computing

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A networking oriented data-driven processor: CUE

International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2002.1035024 ◽

2003 ◽

Cited By ~ 1

Author(s):

H. Nishikawa ◽

R. Kurebayashi

Keyword(s):

Data Driven

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Preliminary evaluation of a binary translation system for multithreaded processors

International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2002.1035021 ◽

2003 ◽

Author(s):

K. Ootsu ◽

T. Yokota ◽

T. Ono ◽

T. Baba

Keyword(s):

Translation System ◽

Preliminary Evaluation ◽

Binary Translation ◽

Multithreaded Processors

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Reducing power with an L0 instruction cache using history-based prediction

International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2002.1035013 ◽

2003 ◽

Cited By ~ 3

Author(s):

Weiyu Tang ◽

A.V. Veidenbaum ◽

A. Nicolau

Keyword(s):

Reducing Power ◽

Instruction Cache

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Design and implementation of interrupt packaging mechanism

International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2002.1035023 ◽

2003 ◽

Author(s):

K. Nakashima ◽

S. Kusakabe ◽

H. Taniguchi ◽

M. Amamiya

Keyword(s):

Design And Implementation

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A low latency high bandwidth network interface prototype for PC cluster

International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2002.1035022 ◽

2003 ◽

Cited By ~ 5

Author(s):

N. Tanabe ◽

Y. Hamada ◽

H. Nakajo ◽

H. Imashiro ◽

J. Yamamoto ◽

...

Keyword(s):

Network Interface ◽

Low Latency ◽

Pc Cluster ◽

High Bandwidth

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Exploring advanced architectures using performance prediction

International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2002.1035016 ◽

2003 ◽

Cited By ~ 9

Author(s):

D.J. Kerbyson ◽

H.J. Wasserman ◽

A. Hoisie

Keyword(s):

Performance Prediction

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Tight non-linear loop timing estimation

International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2002.1035015 ◽

2003 ◽

Author(s):

R.A. van Engelen ◽

K.A. Gallivan

Keyword(s):

Timing Estimation ◽

Non Linear

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Trading bandwidth for latency: managing continuations through a carpet bag cache

International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2002.1035017 ◽

2003 ◽

Cited By ~ 4

Author(s):

R.C. Murphy ◽

P.M. Kogge

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International Workshop on Innovative Architecture for Future Generation High-Performance Processors and SystemsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Power and performance fitting in nanometer design

Architecture and compiler co-optimization for high performance computing

A networking oriented data-driven processor: CUE

Preliminary evaluation of a binary translation system for multithreaded processors

Reducing power with an L0 instruction cache using history-based prediction

Design and implementation of interrupt packaging mechanism

A low latency high bandwidth network interface prototype for PC cluster

Exploring advanced architectures using performance prediction

Tight non-linear loop timing estimation

Trading bandwidth for latency: managing continuations through a carpet bag cache

International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
Latest Publications