Records of the 2003 International Workshop on Memory Technology, Design and Testing
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0769520049

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Applying defect-based test to embedded memories in a COT model

Records of the 2003 International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2003.1222364 ◽

2004 ◽

Cited By ~ 5

Author(s):

R. Aitken

Keyword(s):

Embedded Memories

Download Full-text

ITRS commodity memory roadmap

Records of the 2003 International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2003.1222362 ◽

2004 ◽

Cited By ~ 5

Author(s):

R. Barth

Download Full-text

A 40 ns random access time low voltage 2Mbits EEPROM memory for embedded applications

Records of the 2003 International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2003.1222365 ◽

2004 ◽

Author(s):

J.-M. Daga ◽

C. Papaix ◽

E. Racape ◽

M. Combe ◽

V. Sialelli ◽

...

Keyword(s):

Low Voltage ◽

Random Access ◽

Access Time ◽

Embedded Applications

Download Full-text

Output timing measurement using an Idd method

Records of the 2003 International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2003.1222359 ◽

2004 ◽

Author(s):

J. Vollrath

Keyword(s):

Timing Measurement

Download Full-text

Optimal spare utilization in repairable and reliable memory cores

Records of the 2003 International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2003.1222363 ◽

2004 ◽

Cited By ~ 11

Author(s):

M. Choi ◽

N. Park ◽

F. Lombardi ◽

Y.B. Kim ◽

V. Piuri

Download Full-text

Systematic memory test generation for DRAM defects causing two floating nodes

Records of the 2003 International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2003.1222357 ◽

2004 ◽

Author(s):

Z. Al-Ars ◽

Ad.J. van de Goor

Keyword(s):

Test Generation ◽

Memory Test

Download Full-text

A multilevel DRAM with hierarchical bitlines and serial sensing

Records of the 2003 International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2003.1222355 ◽

2004 ◽

Cited By ~ 2

Author(s):

B.F. Cockburn ◽

J.H. Tapia ◽

D.G. Elliott

Download Full-text

Application specific DRAMs Today

Records of the 2003 International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2003.1222354 ◽

2004 ◽

Cited By ~ 4

Author(s):

B. Prince

Keyword(s):

Application Specific

Download Full-text

A testability-driven optimizer and wrapper generator for embedded memories

Records of the 2003 International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2003.1222361 ◽

2004 ◽

Author(s):

Rei-Fu Huang ◽

Li-Ming Denq ◽

Cheng-Wen Wu ◽

Jin-Fu Li

Keyword(s):

Embedded Memories

Download Full-text

An electrical simulation model for the chalcogenide phase-change memory cell

Records of the 2003 International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2003.1222366 ◽

2004 ◽

Cited By ~ 5

Author(s):

D. Salamon ◽

B.F. Cockburn

Keyword(s):

Phase Change ◽

Simulation Model ◽

Phase Change Memory ◽

Memory Cell ◽

Electrical Simulation ◽

Change Memory

Download Full-text

Records of the 2003 International Workshop on Memory Technology, Design and TestingLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Applying defect-based test to embedded memories in a COT model

ITRS commodity memory roadmap

A 40 ns random access time low voltage 2Mbits EEPROM memory for embedded applications

Output timing measurement using an Idd method

Optimal spare utilization in repairable and reliable memory cores

Systematic memory test generation for DRAM defects causing two floating nodes

A multilevel DRAM with hierarchical bitlines and serial sensing

Application specific DRAMs Today

A testability-driven optimizer and wrapper generator for embedded memories

An electrical simulation model for the chalcogenide phase-change memory cell

Records of the 2003 International Workshop on Memory Technology, Design and Testing
Latest Publications