Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors
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Published By IEEE Comput. Soc

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A component architecture for FPGA-based, DSP system design

Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors ◽

10.1109/asap.2002.1030703 ◽

2003 ◽

Cited By ~ 3

Author(s):

G. Spivey ◽

S.S. Bhattacharyya ◽

K. Nakajima

Keyword(s):

System Design ◽

Component Architecture ◽

Dsp System

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Instruction stream mutation for non-deterministic processors

Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors ◽

10.1109/asap.2002.1030727 ◽

2003 ◽

Cited By ~ 16

Author(s):

J. Irwin ◽

D. Page ◽

N.P. Smart

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High-radix logarithm with selection by rounding

Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors ◽

10.1109/asap.2002.1030708 ◽

2003 ◽

Cited By ~ 12

Author(s):

J.-A. Pineiro ◽

M.D. Ercegovac ◽

J.D. Bruguera

Keyword(s):

High Radix

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Predictable instruction caching for media processors

Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors ◽

10.1109/asap.2002.1030713 ◽

2003 ◽

Cited By ~ 4

Author(s):

J. Irwin ◽

M.D. May ◽

H.L. Muller ◽

D. Page

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A combined interval and floating-point comparator/selector

Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors ◽

10.1109/asap.2002.1030720 ◽

2003 ◽

Cited By ~ 2

Author(s):

A. Akkas

Keyword(s):

Floating Point

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Matrix engine for signal processing applications using the logarithmic number system

Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors ◽

10.1109/asap.2002.1030730 ◽

2003 ◽

Cited By ~ 12

Author(s):

E.I. Chester ◽

J.N. Coleman

Keyword(s):

Signal Processing ◽

Number System ◽

Logarithmic Number System ◽

Logarithmic Number

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Refining instruction set architecture for high-performance multimedia processing in constrained environments

Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors ◽

10.1109/asap.2002.1030724 ◽

2003 ◽

Cited By ~ 5

Author(s):

R.B. Lee ◽

A.M. Fiskiran ◽

Zhijie Shi ◽

Xiao Yang

Keyword(s):

High Performance ◽

Instruction Set ◽

Instruction Set Architecture ◽

Multimedia Processing ◽

Constrained Environments

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Model-based exploration of the design space for heterogeneous systems on chip

Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors ◽

10.1109/asap.2002.1030702 ◽

2003 ◽

Cited By ~ 12

Author(s):

H. Blume ◽

H. Hubert ◽

H.T. Feldkamper ◽

T.G. Noll

Keyword(s):

Design Space ◽

Heterogeneous Systems ◽

Model Based ◽

Systems On Chip ◽

On Chip

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Low power memory design

Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors ◽

10.1109/asap.2002.1030704 ◽

2003 ◽

Author(s):

Wen-Tsong Shiue

Keyword(s):

Low Power ◽

Memory Design

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A mathematical model of trace cache

Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors ◽

10.1109/asap.2002.1030715 ◽

2003 ◽

Cited By ~ 4

Author(s):

A. Hossain ◽

D.J. Pease ◽

J.S. Burns ◽

N. Parveen

Keyword(s):

Mathematical Model ◽

Trace Cache

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Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and ProcessorsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

A component architecture for FPGA-based, DSP system design

Instruction stream mutation for non-deterministic processors

High-radix logarithm with selection by rounding

Predictable instruction caching for media processors

A combined interval and floating-point comparator/selector

Matrix engine for signal processing applications using the logarithmic number system

Refining instruction set architecture for high-performance multimedia processing in constrained environments

Model-based exploration of the design space for heterogeneous systems on chip

Low power memory design

A mathematical model of trace cache

Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors
Latest Publications