Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236)
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE Comput. Soc

0818684941

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Test algorithm for memory cell disturb failures

Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236) ◽

10.1109/mtdt.1998.705946 ◽

2002 ◽

Cited By ~ 2

Author(s):

D. Aadsen ◽

L. Fenstermaker ◽

F. Higgins ◽

Ilyoung Kim ◽

J. Lewandowski ◽

...

Keyword(s):

Memory Cell ◽

Test Algorithm

Download Full-text

An integrated open CAD system for DSP design with embedded memory

Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236) ◽

10.1109/mtdt.1998.705938 ◽

2002 ◽

Author(s):

Xiao Sun

Keyword(s):

Embedded Memory ◽

Cad System

Download Full-text

Tutorial on DRAM fault modeling and test pattern design

Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236) ◽

10.1109/mtdt.1998.705948 ◽

2002 ◽

Cited By ~ 1

Author(s):

B.F. Cockburn

Keyword(s):

Test Pattern ◽

Fault Modeling ◽

Pattern Design

Download Full-text

Converting March tests for bit-oriented memories into tests for word-oriented memories

Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236) ◽

10.1109/mtdt.1998.705945 ◽

2002 ◽

Cited By ~ 24

Author(s):

A.J. Van De Goor ◽

I.B.S. Tlili ◽

S. Hamdioui

Keyword(s):

March Tests

Download Full-text

BIST for word-oriented DRAM

Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236) ◽

10.1109/mtdt.1998.705943 ◽

2002 ◽

Cited By ~ 1

Author(s):

L. Zakrevski ◽

M. Karpovsky ◽

S.H. Yang

Download Full-text

Verification of CAM tests for input stuck-at faults

Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236) ◽

10.1109/mtdt.1998.705951 ◽

2002 ◽

Cited By ~ 4

Author(s):

P.R. Sidorowicz ◽

J.A. Brzozowski

Download Full-text

An SDRAM interface for simplified "at-speed" testing of the SLDRAM internal array

Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236) ◽

10.1109/mtdt.1998.705944 ◽

2002 ◽

Cited By ~ 1

Author(s):

J. Wu ◽

L. Paris ◽

J. Stender ◽

I. Harrison ◽

P. DeMone ◽

...

Download Full-text

A modular embedded DRAM core concept in 0.24 μm technology

Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236) ◽

10.1109/mtdt.1998.705941 ◽

2002 ◽

Cited By ~ 2

Author(s):

K. Schonemann

Keyword(s):

Core Concept

Download Full-text

Integration of non-classical faults in standard March tests

Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236) ◽

10.1109/mtdt.1998.705953 ◽

2002 ◽

Cited By ~ 40

Author(s):

D. Niggemeyer ◽

M. Redeker ◽

J. Otterstedt

Keyword(s):

March Tests

Download Full-text

Memory generator method for sizing transistors in RAM/ROM blocks

Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236) ◽

10.1109/mtdt.1998.705939 ◽

2002 ◽

Cited By ~ 3

Author(s):

D. Donnelly

Download Full-text

Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Test algorithm for memory cell disturb failures

An integrated open CAD system for DSP design with embedded memory

Tutorial on DRAM fault modeling and test pattern design

Converting March tests for bit-oriented memories into tests for word-oriented memories

BIST for word-oriented DRAM

Verification of CAM tests for input stuck-at faults

An SDRAM interface for simplified "at-speed" testing of the SLDRAM internal array

A modular embedded DRAM core concept in 0.24 μm technology

Integration of non-classical faults in standard March tests

Memory generator method for sizing transistors in RAM/ROM blocks

Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236)
Latest Publications