Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211)
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Scaling and performance implications for power supply and other signal routing constraints imposed by I/O pad limitations

Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211) ◽

10.1109/ipdi.1998.663619 ◽

2002 ◽

Cited By ~ 7

Author(s):

L.A. Jr. Arledge ◽

W.T. Lynch

Keyword(s):

Power Supply ◽

And Performance ◽

Signal Routing

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Trends in BGA design methodologies

Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211) ◽

10.1109/ipdi.1998.663643 ◽

2002 ◽

Cited By ~ 2

Author(s):

K. Rinebold ◽

W. Newberry

Keyword(s):

Design Methodologies

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Parasitic characteristics of BGA packages

Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211) ◽

10.1109/ipdi.1998.663644 ◽

2002 ◽

Cited By ~ 4

Author(s):

T. Chang ◽

P.H. Cheng ◽

H.C. Huang ◽

R.S. Lee ◽

R. Lo

Keyword(s):

Bga Packages

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Shorting via arrays for the elimination of package resonance to reduce power supply noise in multi-layered area-array IC packages

Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211) ◽

10.1109/ipdi.1998.663642 ◽

2002 ◽

Cited By ~ 14

Author(s):

J. Fang ◽

J. Zhao ◽

J. Zhang

Keyword(s):

Power Supply ◽

Power Supply Noise ◽

Area Array ◽

Supply Noise

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Understanding models of substrate behaviour for the routing of high I/O packages

Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211) ◽

10.1109/ipdi.1998.663622 ◽

2002 ◽

Cited By ~ 2

Author(s):

P.J. Palmer ◽

D.J. Williams

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Implications of area-array I/O for row-based placement methodology

Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211) ◽

10.1109/ipdi.1998.663636 ◽

2002 ◽

Cited By ~ 14

Author(s):

A. Caldwell ◽

A.B. Kahng ◽

S. Mantik ◽

I.L. Markov

Keyword(s):

Area Array

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Order reduction of high-speed interconnect electrical models: The issue of passivity

Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211) ◽

10.1109/ipdi.1998.663645 ◽

2002 ◽

Cited By ~ 8

Author(s):

A.C. Cangellaris ◽

M. Celik

Keyword(s):

High Speed ◽

Order Reduction

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Error estimation of reduced-order modeling of high speed RLCG circuit

Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211) ◽

10.1109/ipdi.1998.663647 ◽

2002 ◽

Author(s):

N. Lu ◽

I.N. Hajj

Keyword(s):

Error Estimation ◽

High Speed ◽

Reduced Order Modeling ◽

Reduced Order

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Integrated memory/network architectures for cluster-organized, parallel DSP architectures

Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211) ◽

10.1109/ipdi.1998.663615 ◽

2002 ◽

Author(s):

S.K. Tewksbury ◽

V. Gandakota ◽

K. Devabattini ◽

P. Adabala

Keyword(s):

Network Architectures ◽

Memory Network

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Vector compaction for efficient simulation-based power estimation [CMOS design]

Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211) ◽

10.1109/ipdi.1998.663646 ◽

2002 ◽

Cited By ~ 3

Author(s):

R. Radjassamy ◽

J.D. Carothers

Keyword(s):

Power Estimation ◽

Efficient Simulation ◽

Cmos Design ◽

Simulation Based

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Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Scaling and performance implications for power supply and other signal routing constraints imposed by I/O pad limitations

Trends in BGA design methodologies

Parasitic characteristics of BGA packages

Shorting via arrays for the elimination of package resonance to reduce power supply noise in multi-layered area-array IC packages

Understanding models of substrate behaviour for the routing of high I/O packages

Implications of area-array I/O for row-based placement methodology

Order reduction of high-speed interconnect electrical models: The issue of passivity

Error estimation of reduced-order modeling of high speed RLCG circuit

Integrated memory/network architectures for cluster-organized, parallel DSP architectures

Vector compaction for efficient simulation-based power estimation [CMOS design]

Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211)
Latest Publications