Digest of Papers IEEE International Workshop on IDDQ Testing
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Published By IEEE Comput. Soc

0818681233

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Current-mode techniques for self-testing analogue circuits

Digest of Papers IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1997.633010 ◽

2002 ◽

Cited By ~ 1

Author(s):

I. Baturone ◽

S. Sanchez-Solano ◽

A.M. Richardson ◽

J.L. Huertas

Keyword(s):

Current Mode ◽

Self Testing ◽

Analogue Circuits

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Detecting bridging faults in dynamic CMOS circuits

Digest of Papers IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1997.633022 ◽

2002 ◽

Cited By ~ 11

Author(s):

J.T.-Y. Chang ◽

E.J. McCluskey

Keyword(s):

Cmos Circuits ◽

Bridging Faults

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A high-speed low-voltage built-in current sensor

Digest of Papers IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1997.633020 ◽

2002 ◽

Cited By ~ 9

Author(s):

Tsung-Chu Huang ◽

Min-Cheng Huang ◽

Kuen-Jong Lee

Keyword(s):

High Speed ◽

Low Voltage ◽

Current Sensor

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I/sub DDQ/ testable dynamic PLAs

Digest of Papers IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1997.633007 ◽

2002 ◽

Cited By ~ 3

Author(s):

M. Sachdev ◽

H. Kerkhoff

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Sequential circuit test generation for IDDQ testing of bridging faults

Digest of Papers IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1997.633006 ◽

2002 ◽

Cited By ~ 9

Author(s):

Y. Higamit ◽

T. Maeda ◽

K. Kinoshita

Keyword(s):

Test Generation ◽

Sequential Circuit ◽

Bridging Faults ◽

Iddq Testing

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A comprehensive wafer oriented test evaluation (WOTE) scheme for the IDDQ testing of deep sub-micron technologies

Digest of Papers IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1997.633011 ◽

2002 ◽

Cited By ~ 19

Author(s):

A.D. Singh

Keyword(s):

Test Evaluation ◽

Iddq Testing

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A hybrid (logic+I/sub DDQ/) testing strategy using an iterative bridging fault filtering scheme

Digest of Papers IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1997.633015 ◽

2002 ◽

Author(s):

Tzuhao Chen ◽

I.N. Hajj

Keyword(s):

Hybrid Logic ◽

Testing Strategy ◽

Bridging Fault

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Estimation of partition size for I/sub DDQ/ testing using built-in current sensing

Digest of Papers IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1997.633016 ◽

2002 ◽

Cited By ~ 2

Author(s):

S.M. Menon ◽

M. Palmgren

Keyword(s):

Current Sensing ◽

Partition Size

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I/sub CCQ/: a test method for analogue VLSI based on current monitoring

Digest of Papers IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1997.633008 ◽

2002 ◽

Cited By ~ 15

Author(s):

J.P.M. van Lammeren

Keyword(s):

Test Method ◽

Analogue Vlsi ◽

Current Monitoring

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A simulation-based method for estimating defect-free I/sub DDQ/

Digest of Papers IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1997.633018 ◽

2002 ◽

Cited By ~ 15

Author(s):

P.C. Maxwell ◽

J.R. Rearick

Keyword(s):

Simulation Based

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Digest of Papers IEEE International Workshop on IDDQ TestingLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Current-mode techniques for self-testing analogue circuits

Detecting bridging faults in dynamic CMOS circuits

A high-speed low-voltage built-in current sensor

I/sub DDQ/ testable dynamic PLAs

Sequential circuit test generation for IDDQ testing of bridging faults

A comprehensive wafer oriented test evaluation (WOTE) scheme for the IDDQ testing of deep sub-micron technologies

A hybrid (logic+I/sub DDQ/) testing strategy using an iterative bridging fault filtering scheme

Estimation of partition size for I/sub DDQ/ testing using built-in current sensing

I/sub CCQ/: a test method for analogue VLSI based on current monitoring

A simulation-based method for estimating defect-free I/sub DDQ/

Digest of Papers IEEE International Workshop on IDDQ Testing
Latest Publications