2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)
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Published By IEEE

9781479960163

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Improved read and write margins using a novel 8T-SRAM cell

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2014.7004186 ◽

2014 ◽

Cited By ~ 4

Author(s):

Farshad Moradi ◽

Jens K. Madsen

Keyword(s):

Sram Cell

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Backplane/FDA correlation-FDA replacing commercial backplanes for SoC ethernet electrical validation

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2014.7004190 ◽

2014 ◽

Author(s):

Jesus-Andres Mendoza-Bonilla ◽

Alejandro Cortez-Ibarra ◽

Edgar-Andrei Vega-Ochoa ◽

Francisco Rangel-Patino ◽

Brandon Gore

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Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2014.7004185 ◽

2014 ◽

Cited By ~ 2

Author(s):

Moon Gi Seok ◽

Dae Jin Park ◽

Geun Rae Cho ◽

Tag Gon Kim

Keyword(s):

Mixed Model

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A low power 720p motion estimation processor with 3D stacked memory

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2014.7004163 ◽

2014 ◽

Cited By ~ 2

Author(s):

Shuping Zhang ◽

Jinjia Zhou ◽

Dajiang Zhou ◽

Satoshi Goto

Keyword(s):

Motion Estimation ◽

Low Power ◽

Stacked Memory

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Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2014.7004195 ◽

2014 ◽

Author(s):

G. Bruni ◽

P. Rech ◽

L. Tambara ◽

G. L. Nazar ◽

F. L. Kastensmidt ◽

...

Keyword(s):

Power Dissipation

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Advances on the state of the art in QDI design

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2014.7004169 ◽

2014 ◽

Author(s):

Matheus T. Moreira ◽

Ney L. V. Calazans

Keyword(s):

State Of The Art ◽

The State

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Simulated annealing-based placement for microfluidic large scale integration (mLSI) chips

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2014.7004170 ◽

2014 ◽

Cited By ~ 11

Author(s):

Jeffrey McDaniel ◽

Brendon Parker ◽

Philip Brisk

Keyword(s):

Simulated Annealing ◽

Large Scale ◽

Large Scale Integration ◽

Scale Integration

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Optimized active and power-down mode refresh control in 3D-DRAMs

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2014.7004159 ◽

2014 ◽

Cited By ~ 9

Author(s):

Matthias Jung ◽

Christian Weis ◽

Norbert Wehn ◽

Mohammadsadegh Sadri ◽

Luca Benini

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Reconfigurable forward homography estimation system for real-time applications

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2014.7004161 ◽

2014 ◽

Author(s):

Vladan Popovic ◽

Yusuf Leblebici

Keyword(s):

Real Time ◽

Homography Estimation ◽

Real Time Applications ◽

Estimation System

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Implementation of power efficient multicore FFT datapaths by reordering the twiddle factors

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2014.7004162 ◽

2014 ◽

Cited By ~ 1

Author(s):

Sidinei Ghissoni ◽

Eduardo A. C. da Costa ◽

Angelo Goncalves da Luz

Keyword(s):

Power Efficient

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2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Improved read and write margins using a novel 8T-SRAM cell

Backplane/FDA correlation-FDA replacing commercial backplanes for SoC ethernet electrical validation

Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability

A low power 720p motion estimation processor with 3D stacked memory

Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity

Advances on the state of the art in QDI design

Simulated annealing-based placement for microfluidic large scale integration (mLSI) chips

Optimized active and power-down mode refresh control in 3D-DRAMs

Reconfigurable forward homography estimation system for real-time applications

Implementation of power efficient multicore FFT datapaths by reordering the twiddle factors

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)
Latest Publications