Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits - Frontiers in Electronic Testing
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Defect-Oriented Analog Testing

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits - Frontiers in Electronic Testing ◽

10.1007/0-387-46547-2_6 ◽

2007 ◽

pp. 225-287

Author(s):

Manoj Sachdev ◽

José Pineda de Gyvez

Keyword(s):

Analog Testing

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Functional and Parametric Defect Models

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits - Frontiers in Electronic Testing ◽

10.1007/0-387-46547-2_2 ◽

2007 ◽

pp. 23-67

Author(s):

Manoj Sachdev ◽

José Pineda de Gyvez

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Introduction

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits - Frontiers in Electronic Testing ◽

10.1007/0-387-46547-2_1 ◽

2007 ◽

pp. 1-22

Author(s):

Manoj Sachdev ◽

José Pineda de Gyvez

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Yield Engineering

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits - Frontiers in Electronic Testing ◽

10.1007/0-387-46547-2_7 ◽

2007 ◽

pp. 289-315

Author(s):

Manoj Sachdev ◽

José Pineda de Gyvez

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Defects in Logic Circuits and their Test Implications

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits - Frontiers in Electronic Testing ◽

10.1007/0-387-46547-2_4 ◽

2007 ◽

pp. 111-150

Author(s):

Manoj Sachdev ◽

José Pineda de Gyvez

Keyword(s):

Logic Circuits

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Digital CMOS Fault Modeling

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits - Frontiers in Electronic Testing ◽

10.1007/0-387-46547-2_3 ◽

2007 ◽

pp. 69-110

Author(s):

Manoj Sachdev ◽

José Pineda de Gyvez

Keyword(s):

Fault Modeling ◽

Digital Cmos

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Conclusion

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits - Frontiers in Electronic Testing ◽

10.1007/0-387-46547-2_8 ◽

2007 ◽

pp. 317-324

Author(s):

Manoj Sachdev ◽

José Pineda de Gyvez

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Testing Defects and Parametric Variations in RAMs

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits - Frontiers in Electronic Testing ◽

10.1007/0-387-46547-2_5 ◽

2007 ◽

pp. 151-223

Author(s):

Manoj Sachdev ◽

José Pineda de Gyvez

Download Full-text

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits - Frontiers in Electronic TestingLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer US

Defect-Oriented Analog Testing

Functional and Parametric Defect Models

Introduction

Yield Engineering

Defects in Logic Circuits and their Test Implications

Digital CMOS Fault Modeling

Conclusion

Testing Defects and Parametric Variations in RAMs

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits - Frontiers in Electronic Testing
Latest Publications