2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)
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2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) ◽

10.1109/h2rc49586.2019.00003 ◽

2019 ◽

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The Memory Controller Wall: Benchmarking the Intel FPGA SDK for OpenCL Memory Interface

2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) ◽

10.1109/h2rc49586.2019.00007 ◽

2019 ◽

Cited By ~ 1

Author(s):

Hamid Reza Zohouri ◽

Satoshi Matsuoka

Keyword(s):

Memory Controller ◽

Memory Interface

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Implementation and Impact of an Ultra-Compact Multi-FPGA Board for Large System Prototyping

2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) ◽

10.1109/h2rc49586.2019.00010 ◽

2019 ◽

Cited By ~ 1

Author(s):

Fabien Chaix ◽

Georgios Ailamakis ◽

Theocharis Vavouris ◽

Astrinos Damianakis ◽

Manolis Katevenis ◽

...

Keyword(s):

Large System

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It's All About Data Movement: Optimising FPGA Data Access to Boost Performance

2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) ◽

10.1109/h2rc49586.2019.00006 ◽

2019 ◽

Cited By ~ 1

Author(s):

Nick Brown ◽

David Dolman

Keyword(s):

Data Access ◽

Data Movement

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Performance and Energy Efficiency Analysis of Reverse Time Migration on a FPGA Platform

2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) ◽

10.1109/h2rc49586.2019.00012 ◽

2019 ◽

Author(s):

Joao Carlos Bittencourt ◽

Joaquim Ranyere Oliveira ◽

Anderson Nascimento ◽

Rodrigo Tutu ◽

Laue Rami Jesus ◽

...

Keyword(s):

Energy Efficiency ◽

Efficiency Analysis ◽

Reverse Time ◽

Reverse Time Migration ◽

Time Migration ◽

Energy Efficiency Analysis

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Organization

2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) ◽

10.1109/h2rc49586.2019.00005 ◽

2019 ◽

Download Full-text

Message from the Workshop Chairs

2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) ◽

10.1109/h2rc49586.2019.00004 ◽

2019 ◽

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[Title page]

2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) ◽

10.1109/h2rc49586.2019.00001 ◽

2019 ◽

Keyword(s):

Title Page

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High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud

2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) ◽

10.1109/h2rc49586.2019.00009 ◽

2019 ◽

Author(s):

Micha Ober ◽

Jaco Hofmann ◽

Lukas Sommer ◽

Lukas Weber ◽

Andreas Koch

Keyword(s):

High Throughput ◽

Network Inference

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Combining Perfect Shuffle and Bitonic Networks for Efficient Quantum Sorting

2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) ◽

10.1109/h2rc49586.2019.00011 ◽

2019 ◽

Cited By ~ 1

Author(s):

Naveed Mahmud ◽

Bailey Srimoungchanh ◽

Bennett Haase-Divine ◽

Nolan Blankenau ◽

Annika Kuhnke ◽

...

Keyword(s):

Perfect Shuffle

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2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Table of contents

The Memory Controller Wall: Benchmarking the Intel FPGA SDK for OpenCL Memory Interface

Implementation and Impact of an Ultra-Compact Multi-FPGA Board for Large System Prototyping

It's All About Data Movement: Optimising FPGA Data Access to Boost Performance

Performance and Energy Efficiency Analysis of Reverse Time Migration on a FPGA Platform

Organization

Message from the Workshop Chairs

[Title page]

High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud

Combining Perfect Shuffle and Bitonic Networks for Efficient Quantum Sorting

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2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Table of contents

The Memory Controller Wall: Benchmarking the Intel FPGA SDK for OpenCL Memory Interface

Implementation and Impact of an Ultra-Compact Multi-FPGA Board for Large System Prototyping

It's All About Data Movement: Optimising FPGA Data Access to Boost Performance

Performance and Energy Efficiency Analysis of Reverse Time Migration on a FPGA Platform

Organization

Message from the Workshop Chairs

[Title page]

High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud

Combining Perfect Shuffle and Bitonic Networks for Efficient Quantum Sorting

2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)
Latest Publications