Digest of Papers 1996 IEEE International Workshop on IDDQ Testing
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Published By IEEE Comput. Soc. Press

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An efficient I/sub DDQ/ test generation scheme for bridging faults in CMOS digital circuits

Digest of Papers 1996 IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1996.557833 ◽

2002 ◽

Cited By ~ 9

Author(s):

Tzuhao Chen ◽

I.N. Hajj ◽

E.M. Rudnick ◽

J.H. Patel

Keyword(s):

Test Generation ◽

Digital Circuits ◽

Bridging Faults

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Test of CMOS circuits based on its energy consumption

Digest of Papers 1996 IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1996.557809 ◽

2002 ◽

Cited By ~ 1

Author(s):

M.A. Ortega ◽

J. Rius ◽

J. Figueras

Keyword(s):

Energy Consumption ◽

Cmos Circuits

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Feasibility of employing an I/sub DDQ/ output amplifier in deep submicron built-in current sensors

Digest of Papers 1996 IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1996.557822 ◽

2002 ◽

Cited By ~ 1

Author(s):

S.P. Athan ◽

D.L. Landis

Keyword(s):

Deep Submicron ◽

Output Amplifier ◽

Current Sensors

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Testing the realistic bridging faults in CMOS circuits

Digest of Papers 1996 IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1996.557838 ◽

2002 ◽

Author(s):

Peilin Song ◽

Jien-Chung Lo

Keyword(s):

Cmos Circuits ◽

Bridging Faults

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Automatic test pattern generation for Iddq faults based upon symbolic simulation

Digest of Papers 1996 IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1996.557840 ◽

2002 ◽

Author(s):

L. Ribas-Xirgo ◽

J. Carrabina-Bordoll

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Automatic Test Pattern Generation ◽

Symbolic Simulation ◽

Automatic Test

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Low cost test solution for IDDQ

Digest of Papers 1996 IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1996.557813 ◽

2002 ◽

Cited By ~ 2

Author(s):

B. Thomas ◽

R. Andlauer

Keyword(s):

Low Cost ◽

Test Solution

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Implementation of a BIC monitor in a new analog BIST structure

Digest of Papers 1996 IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1996.557817 ◽

2002 ◽

Cited By ~ 6

Author(s):

M. Sidiropulos ◽

V. Stopjakova ◽

H. Manhaeve

Keyword(s):

Analog Bist

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Realistic defect coverages of voltage and current tests

Digest of Papers 1996 IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1996.557798 ◽

2002 ◽

Cited By ~ 6

Author(s):

F. Peters ◽

S. Oostdijk

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Standard cell library characterization for setting current limits for I/sub DDQ/ testing

Digest of Papers 1996 IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1996.557810 ◽

2002 ◽

Cited By ~ 4

Author(s):

S.D. Millman ◽

J.M. Acken

Keyword(s):

Standard Cell ◽

Standard Cell Library ◽

Cell Library ◽

Library Characterization

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The effectiveness of IDDQ and high voltage stress for burn-in elimination [CMOS production]

Digest of Papers 1996 IEEE International Workshop on IDDQ Testing ◽

10.1109/iddq.1996.557800 ◽

2002 ◽

Cited By ~ 18

Author(s):

R. Kawahara ◽

O. Nakayama ◽

T. Kurasawa

Keyword(s):

High Voltage ◽

Voltage Stress

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Digest of Papers 1996 IEEE International Workshop on IDDQ TestingLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

An efficient I/sub DDQ/ test generation scheme for bridging faults in CMOS digital circuits

Test of CMOS circuits based on its energy consumption

Feasibility of employing an I/sub DDQ/ output amplifier in deep submicron built-in current sensors

Testing the realistic bridging faults in CMOS circuits

Automatic test pattern generation for Iddq faults based upon symbolic simulation

Low cost test solution for IDDQ

Implementation of a BIC monitor in a new analog BIST structure

Realistic defect coverages of voltage and current tests

Standard cell library characterization for setting current limits for I/sub DDQ/ testing

The effectiveness of IDDQ and high voltage stress for burn-in elimination [CMOS production]

Digest of Papers 1996 IEEE International Workshop on IDDQ Testing
Latest Publications