Proceedings of 21 International Symposium on Computer Architecture
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Published By IEEE Comput. Soc. Press

0818655100

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The Stanford FLASH multiprocessor

Proceedings of 21 International Symposium on Computer Architecture ◽

10.1109/isca.1994.288140 ◽

2002 ◽

Cited By ~ 233

Author(s):

J. Kuskin ◽

D. Ofelt ◽

M. Heinrich ◽

J. Heinlein ◽

R. Simoni ◽

...

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Complexity/performance tradeoffs with non-blocking loads

Proceedings of 21 International Symposium on Computer Architecture ◽

10.1109/isca.1994.288148 ◽

2002 ◽

Cited By ~ 26

Author(s):

K.I. Farkas ◽

N.P. Jouppi

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A performance study of software and hardware data prefetching schemes

Proceedings of 21 International Symposium on Computer Architecture ◽

10.1109/isca.1994.288147 ◽

2002 ◽

Cited By ~ 54

Author(s):

Tien-Fu Chen ◽

J.-L. Baer

Keyword(s):

Data Prefetching ◽

Performance Study ◽

Software And Hardware ◽

A Performance

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Measurement-based characterization of global memory and network contention, operating system and parallelisation overheads: case study on a shared-memory multiprocessor

Proceedings of 21 International Symposium on Computer Architecture ◽

10.1109/isca.1994.288160 ◽

2002 ◽

Cited By ~ 2

Author(s):

C. Natarajan ◽

S. Sharma ◽

R.K. Iyer

Keyword(s):

Operating System ◽

Shared Memory ◽

Global Memory ◽

Shared Memory Multiprocessor ◽

Network Contention

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Tradeoffs in two-level on-chip caching

Proceedings of 21 International Symposium on Computer Architecture ◽

10.1109/isca.1994.288163 ◽

2002 ◽

Cited By ~ 59

Author(s):

N.P. Jouppi ◽

S.J.E. Wilton

Keyword(s):

On Chip

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Guarded execution and branch prediction in dynamic ILP processors

Proceedings of 21 International Symposium on Computer Architecture ◽

10.1109/isca.1994.288156 ◽

2002 ◽

Cited By ~ 35

Author(s):

D.N. Pnevmatikatos ◽

G.S. Sohi

Keyword(s):

Branch Prediction

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Architectural support for performance tuning: a case study on the SPARCcenter 2000

Proceedings of 21 International Symposium on Computer Architecture ◽

10.1109/isca.1994.288162 ◽

2002 ◽

Cited By ~ 1

Author(s):

A. Singhal ◽

A.J. Goldberg

Keyword(s):

Performance Tuning ◽

Architectural Support

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A comparison of message passing and shared memory architectures for data parallel programs

Proceedings of 21 International Symposium on Computer Architecture ◽

10.1109/isca.1994.288158 ◽

2002 ◽

Cited By ~ 7

Author(s):

A.C. Klaiber ◽

H.M. Levy

Keyword(s):

Shared Memory ◽

Message Passing ◽

Parallel Programs ◽

Data Parallel ◽

Memory Architectures ◽

Shared Memory Architectures

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Software-extended coherent shared memory: performance and cost

Proceedings of 21 International Symposium on Computer Architecture ◽

10.1109/isca.1994.288139 ◽

2002 ◽

Cited By ~ 15

Author(s):

D. Chaiken ◽

A. Agarwal

Keyword(s):

Shared Memory ◽

Memory Performance

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Decoupled sectored caches: conciliating low tag implementation cost and low miss ratio

Proceedings of 21 International Symposium on Computer Architecture ◽

10.1109/isca.1994.288133 ◽

2002 ◽

Cited By ~ 42

Author(s):

A. Seznec

Keyword(s):

Implementation Cost

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Proceedings of 21 International Symposium on Computer ArchitectureLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

The Stanford FLASH multiprocessor

Complexity/performance tradeoffs with non-blocking loads

A performance study of software and hardware data prefetching schemes

Measurement-based characterization of global memory and network contention, operating system and parallelisation overheads: case study on a shared-memory multiprocessor

Tradeoffs in two-level on-chip caching

Guarded execution and branch prediction in dynamic ILP processors

Architectural support for performance tuning: a case study on the SPARCcenter 2000

A comparison of message passing and shared memory architectures for data parallel programs

Software-extended coherent shared memory: performance and cost

Decoupled sectored caches: conciliating low tag implementation cost and low miss ratio

Proceedings of 21 International Symposium on Computer Architecture
Latest Publications