VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - IFIP Advances in Information and Communication Technology
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Published By Springer International Publishing

9783030234249, 9783030234256

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ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code

VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-030-23425-6_7 ◽

2019 ◽

pp. 128-146

Author(s):

Swagata Mandal ◽

Yaswanth Tavva ◽

Debjyoti Bhattacharjee ◽

Anupam Chattopadhyay

Keyword(s):

Bch Code

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The Connection Layout in a Lattice of Four-Terminal Switches

VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-030-23425-6_3 ◽

2019 ◽

pp. 32-52

Author(s):

Anna Bernasconi ◽

Antonio Boffa ◽

Fabrizio Luccio ◽

Linda Pagli

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Rectification of Arithmetic Circuits with Craig Interpolants in Finite Fields

VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-030-23425-6_5 ◽

2019 ◽

pp. 79-106

Author(s):

Utkarsh Gupta ◽

Irina Ilioaea ◽

Vikas Rao ◽

Arpitha Srinath ◽

Priyank Kalla ◽

...

Keyword(s):

Finite Fields ◽

Arithmetic Circuits

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Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS

VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-030-23425-6_4 ◽

2019 ◽

pp. 53-78

Author(s):

L. Stornaiuolo ◽

M. Rabozzi ◽

M. D. Santambrogio ◽

D. Sciuto ◽

C. B. Ciobanu ◽

...

Keyword(s):

High Performance ◽

Parallel Memories

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Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Performance Analysis

VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-030-23425-6_9 ◽

2019 ◽

pp. 167-186

Author(s):

Francesco Barchi ◽

Gianvito Urgese ◽

Enrico Macii ◽

Andrea Acquaviva

Keyword(s):

Neural Networks ◽

Performance Analysis ◽

Problem Formulation ◽

Spiking Neural Networks ◽

And Performance

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Efficient Hardware/Software Co-design for NTRU

VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-030-23425-6_13 ◽

2019 ◽

pp. 257-280

Author(s):

Tim Fritzmann ◽

Thomas Schamberger ◽

Christoph Frisch ◽

Konstantin Braun ◽

Georg Maringer ◽

...

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Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection

VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-030-23425-6_11 ◽

2019 ◽

pp. 207-231

Author(s):

Victor Champac ◽

Andres Gomez ◽

Freddy Forero ◽

Kaushik Roy

Keyword(s):

Process Variations

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Correction to: Improved Test Solutions for COTS-Based Systems in Space Applications

VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-030-23425-6_14 ◽

2019 ◽

pp. C1-C1

Author(s):

Riccardo Cantoro ◽

Sara Carbonara ◽

Andrea Floridia ◽

Ernesto Sanchez ◽

Matteo Sonza Reorda ◽

...

Keyword(s):

Space Applications

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A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load

VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-030-23425-6_1 ◽

2019 ◽

pp. 1-13

Author(s):

Naoki Ojima ◽

Toru Nakura ◽

Tetsuya Iizuka ◽

Kunihiro Asada

Keyword(s):

Current Efficiency ◽

Low Dropout Regulator

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Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis

VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-030-23425-6_6 ◽

2019 ◽

pp. 107-127

Author(s):

Valentino Peluso ◽

Andrea Calimera

Keyword(s):

Neural Networks ◽

Convolutional Neural Networks ◽

Deep Convolutional Neural Networks ◽

Pareto Analysis

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VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - IFIP Advances in Information and Communication TechnologyLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer International Publishing

ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code

The Connection Layout in a Lattice of Four-Terminal Switches

Rectification of Arithmetic Circuits with Craig Interpolants in Finite Fields

Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS

Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Performance Analysis

Efficient Hardware/Software Co-design for NTRU

Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection

Correction to: Improved Test Solutions for COTS-Based Systems in Space Applications

A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load

Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis

VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - IFIP Advances in Information and Communication Technology
Latest Publications