Indirect cutting tool wear classification using deep learning and chip colour analysis

In the growing Industry 4.0 market, there is strong need to implement automatic inspection methods to support manufacturing processes. Tool wear in turning is one of the biggest concerns that most expert operators are able to indirectly infer through the analysis of the removed chips. Automatising this operation would enable developing more efficient cutting processes that turns in easier process planning management toward the Zero Defect Manufacturing paradigm. This paper presents a deep learning approach, based on image processing applied to turning chips for indirectly identifying tool wear levels. The procedure extracts different indicators from the RGB and HSV image channels and instructs a neural network for classifying the chips, based on tool state conditions. Images were collected with a high-resolution digital camera during an experimental cutting campaign involving tool wear analysis with direct microscope imaging. The sensitivity analysis confirmed that the most sensible image channels are the hue value H that were used to teach the network, leading to performances in the range of 95 of proper classification. The feasibility of the deep learning approach for indirectly understanding the tool wear from the chip colour characterisation is confirmed. However, due to the big effects on chip colours of variables as the workpiece material and cutting process parameters, the applicability is limited to stable production flows. An industrial implementation can be foreseen by populating proper large databases and by implementing real-time chip segmentation analysis.

Molecular Dynamics Study of the Effect of Abrasive Grains Orientation and Spacing during Nanogrinding

Grinding at the nanometric level can be efficiently employed for the creation of surfaces with ultrahigh precision by removing a few atomic layers from the substrate. However, since measurements at this level are rather difficult, numerical investigation can be conducted in order to reveal the mechanisms of material removal during nanogrinding. In the present study, a Molecular Dynamics model with multiple abrasive grains is developed in order to determine the effect of spacing between the adjacent rows of abrasive grains and the effect of the rake angle of the abrasive grains on the grinding forces and temperatures, ground surface, and chip formation and also, subsurface damage of the substrate. Findings indicate that nanogrinding with abrasive grains situated in adjacent rows with spacing of 1 Å leads directly to a flat surface and the amount of material remaining between the rows of grains remains minimal for spacing values up to 5 Å. Moreover, higher negative rake angle of the grains leads to higher grinding forces and friction coefficient values over 1.0 for angles larger than −40°. At the same time, chip formation is suppressed and plastic deformation increases with larger negative rake angles, due to higher compressive action of the abrasive grains.

Electron Beam Probing of Active Advanced FinFET Circuit with Fin Level Resolution

This paper shows for the first time chip level electron beam probing on fully functional 10nm and 14nm node FinFET chips with sub-fin level resolution using techniques developed in house. Three novel electron beam probing techniques were developed and used in the debug and fault isolation of advanced node semiconductor devices. These techniques were E-beam logic state imaging, electron-beam signal image mapping, and E-beam device perturbation. Two tools that can offer all three techniques were constructed and used in production. The techniques have been successfully applied to real case chip debug and fault isolation on advanced 10nm and 14nm FinFET on production tools developed in-house. Sub-fin level resolution was achieved for the first time.

Enhancer regions show high histone H3.3 turnover that changes during differentiation

The organization of DNA into chromatin is dynamic; nucleosomes are frequently displaced to facilitate the ability of regulatory proteins to access specific DNA elements. To gain insight into nucleosome dynamics, and to follow how dynamics change during differentiation, we used a technique called time-ChIP to quantitatively assess histone H3.3 turnover genome-wide during differentiation of mouse ESCs. We found that, without prior assumptions, high turnover could be used to identify regions involved in gene regulation. High turnover was seen at enhancers, as observed previously, with particularly high turnover at super-enhancers. In contrast, regions associated with the repressive Polycomb-Group showed low turnover in ESCs. Turnover correlated with DNA accessibility. Upon differentiation, numerous changes in H3.3 turnover rates were observed, the majority of which occurred at enhancers. Thus, time-ChIP measurement of histone turnover shows that active enhancers are unusually dynamic in ESCs and changes in highly dynamic nucleosomes predominate at enhancers during differentiation.

Modeling Simplification for Thermal Mechanical Analysis of High Density Chip-to-Substrate Connections

Finite element modeling (FEM) is an important component in the design of reliable chip-to-substrate connections. However, FEM can quickly become complex as the number of input/output connections increases. Three-dimensional (3D) chip-substrate models are usually simplified where only portions of the chip-substrate structure is considered in order to conserve computer resources and time. Chip symmetry is often used to simplify the models from full-chip structures to quarter or octant models. Recently, an even simpler 3D model, general plane deformation (GPD) slice model, has been used to characterize the properties of the full-chip and local regions on the structures, such as in the structures for solder ball fatigue. In this study, the accuracy of the GPD model is examined by comparing the mechanical behavior of a flip-chip, copper pillar package from various full and partial chip models to that of the GDP model. In addition, it is shown that the GPD model can be further simplified to a half-GPD model by using the symmetry plane in the middle of the slice and choosing the proper boundary conditions. The number of nodes required for each model and the accuracy of the different FEM models are compared. Analysis of the maximum stress in the silicon chip shows that the full-chip model, quarter model, and octant model all convergence to the same result. However, the GPD and half-GPD models, with the previously used boundary conditions, converge to a different stress values from that of the full-chip models. The error in the GPD models for small, 36 I/O package was 4.7% compared to the more complete, full-chip FEM models. The displacement error in the GPD models was more than 50%, compared to the full-chip models, and increased with larger structures. The high displacement error of the GPD models was due to the ordinarily used boundary conditions which neglect the effect from adjacent I/O on the sidewall of the GPD slice. An optimization equation is proposed to account for the spatial variation in the stress on the GPD sidewall. The GPD displacement error was reduced from 50% to 3.3% for the 36 pillar array.