The Progress of Composites with High Thermal Conductivity and Electromagnetic Shielding

<p>As electronic components develop toward high power, high package density, and device size miniaturization, heat dissipation and electromagnetic interference between electronic components are becoming more and more serious. In order to solve the adverse elec tromagnetic waves and heat radiation generated by electronic devices, people have high hopes for electronic packaging materials with high thermal conductivity and electromagnetic interference resistance. This paper summa rizes the research status of high thermal conductivity composite materials and electromagnetic shielding composite materials. Finally, the latest research results of high thermal conductivity and electromagnetic shielding composites are introduced, and the future development trend of new materials for microelectronic packaging is prospected.</p>

Coupled Thermal and Structural Parametric Analysis of TSVs in 3D Electronics

The convergence and miniaturization of the consumer electronic products such as cell phones and digital cameras has led to the vertical integration of packages i.e., 3-D packaging. Chip-stacking (3-D) is emerging as a powerful tool that satisfies such Integrated Circuit (IC) package requirements. 3-D technology looks to be the future of hand-held electronics; hence, making it an important research area. Stacked chips are peripherally interconnected through wires; this increases the package size and usually requires an extra “interposer” layer between the chips, causing substantial delays. Due to high package density and chip-stacking on top of each other, heat dissipation from the die becomes a concern. To overcome these thermal challenges and provide better inter-chip and chip-substrate electrical connection, Through Silicon Via (TSV) technology is being implemented in 3-D electronics. Electrical interconnection and heat dissipation improves with the number of TSVs. But, there is a trade-off; TSVs occupy the chip real estate, resulting in reduced silicon efficiency when compared to the baseline (no-TSV) scenario. Coefficient of thermal expansion (CTE) mismatch and reduced chip area causes thermal stresses and may lead to premature chip failures. This can be a major reliability issue. In this paper, a parametric study of the number of TSVs in a test vehicle (TV) consisting of 2 vertically stacked dies and TSVs (between the die and the substrate) has been performed using ANSYS WORKBENCH. A quarter symmetry model has been formulated to study the various cases as a function of number of TSVs. Each die has an area of 5.7mm2 with 0.1-mm thickness and 0.5W power rating. The TSV diameter is 50-μm each with a SiO2 insulation film of 25-μm thickness. Junction temperature and thermal resistance is determined to obtain the best case in terms of temperature distribution on the die. Furthermore, thermo-mechanical analysis is performed for all the TSV configurations and a guideline is proposed based on thermal and structural response.

An Advanced LOCOS-Process for the Sub-50 nm-Region Using Low-Stress PECVD-Silicon Nitrides

The standard Local Oxidation of Silicon (LOCOS) technique uses different oxidation rates of silicon and Low Pressure Chemical Vapour Deposited (LPCVD) silicon nitride in steam ambient to structure the field oxide. Due to different coefficients of thermal expansion a pad oxide is needed at the boundary layer to prevent stress from the substrate. This leads to a lateral diffusion of oxygen, also known as “birds beak”, which limits the minimum structure size to a few 100 nm [1]. When scaling down to this dimension, the Shallow Trench Isolation (STI) has become the standard isolation technique for fabrication of high-performance semiconductors to allow a high package density. Unfortunately the STI-process uses Chemical Mechanical Polishing (CMP) which increases the process complexity and leads to high costs. Therefore a new method which uses a low stress Plasma Enhanced Chemical Vapour Deposited (PECVD) silicon nitride without a pad oxide at the boundary layer will be presented in this paper.

Optimization of thermal distribution in ceramics and LTCC structures applied to sensor elements

Thermal properties of Pt or RuO2 thick‐film heaters made on alumina, aluminum nitride or low temperature co‐fired ceramics (LTCC) were compared in the first step of our work. Special holes to improve the heat distribution were included. Several heater layouts were analysed. The heat distribution was measured by an infrared camera, at different heating power. Second, the optimization of LTCC constructions was carried out. The simple structure of LTCC permitted the achievement of a high package density. It was possible to integrate a heating element made from special thick‐film ink as a buried film, inside a substrate. An important step in our technology was the making of the holes. A pattern of holes (achieved by punching or laser cutting) around the heating area permitted a changeable heat gradient. The quality of lamination and the structure of the buried elements were investigated with an ultrasonic microscope.