Analyzing smartphone innovative development: Evidence from Apple’s iPhone

Subject. We analyze development trends in iPhone by reviewing the way their key technological and economic indicators change. Objectives. We trace patterns and trends in technological and economic indicators of iPhone, correlations of the indicators, and the dependence of the price and SAR on technological indicators. Methods. Following our methodology, we study and model indicators of smartphones. Results. We traced and determined the correlation of technological and economic indicators of iPhone. The article demonstrates how the price and SAR mainly depend on technological indicators of smartphones. Conclusions and Relevance. As the findings show, as the above smartphone gets more technologically sophisticated, i.e. the price and SAR increase, we can expect higher risks for the man and the environment, though the mobile device development trends may still persevere. As seen from the analysis, SAR increases as smartphones have more cores and processor frequency, operation memory, which basically entails higher prices. In the mean time, the above indicators lower as the smartphone dimensions grow (screen diagonal, weight, battery capacity).

Smart Sensor Architectures for Multimedia Sensing in IoMT

Today, a wide range of developments and paradigms require the use of embedded systems characterized by restrictions on their computing capacity, consumption, cost, and network connection. The evolution of the Internet of Things (IoT) towards Industrial IoT (IIoT) or the Internet of Multimedia Things (IoMT), its impact within the 4.0 industry, the evolution of cloud computing towards edge or fog computing, also called near-sensor computing, or the increase in the use of embedded vision, are current examples of this trend. One of the most common methods of reducing energy consumption is the use of processor frequency scaling, based on a particular policy. The algorithms to define this policy are intended to obtain good responses to the workloads that occur in smarthphones. There has been no study that allows a correct definition of these algorithms for workloads such as those expected in the above scenarios. This paper presents a method to determine the operating parameters of the dynamic governor algorithm called Interactive, which offers significant improvements in power consumption, without reducing the performance of the application. These improvements depend on the load that the system has to support, so the results are evaluated against three different loads, from higher to lower, showing improvements ranging from 62% to 26%.

Análise de Características Comportamentais de Aplicações OpenMP para Redução do Consumo de Energia

Performance and energy consumption are fundamental requirements in computer systems. A very frequent challenge is to combine both aspects, searching to keep the high performance computing while consuming less energy. There are a lot of techniques to reduce energy consumption, but in general, they use modern processors resources or they require specific knowledge about application and platform used. In this paper, we propose a library that dynamically changes the processor frequency according to the application's computing behavior, using a previous analysis of its Memory-Bound regions. The results show a reduction of 1,89% in energy consumption for Lulesh application with an increase of 0,09% in runtime when we compare our approach against the governor Ondemand of the Linux Operating System.

A Prototype of Online Dynamic Scaling Scheduler for Real-Time Task based on Virtual Machine

In this paper, we provide an architecture of power-aware scheduler for real-time virtual machine system using dynamic frequency scaling mechanism This architecture provides that how to manage real-time resource and how to control processor frequency. In addition, we propose two scheduling schemes that utilize slack time to adjust processor frequency without violating tasks deadline. Based on the provided architecture, we implement a virtualization framework with online power-aware scheduler using RT-Xen real-time hypervisor and Litmus-RT real-time OS. Our implementation manages entire of real-time resource and processor frequency depending on system policy. For trasferring real-time requirements, we implement an interface using hypercall mechanism. To evaluate provided system, we analyze performance evaluation in various aspects.

A Prototype of Online Dynamic Scaling Scheduler for Real-Time Task based on Virtual Machine

In this paper, we provide an architecture of power-aware scheduler for real-time virtual machine system using dynamic frequency scaling mechanism This architecture provides that how to manage real-time resource and how to control processor frequency. In addition, we propose two scheduling schemes that utilize slack time to adjust processor frequency without violating tasks deadline. Based on the provided architecture, we implement a virtualization framework with online power-aware scheduler using RT-Xen real-time hypervisor and Litmus-RT real-time OS. Our implementation manages entire of real-time resource and processor frequency depending on system policy. For trasferring real-time requirements, we implement an interface using hypercall mechanism. To evaluate provided system, we analyze performance evaluation in various aspects.

Performance Evaluation of SHA-2 Standard vs. SHA-3 Finalists on Two Freescale Platforms

Embedded devices are ubiquitously involved in a large variety of security applications which heavily rely on the computation of hash functions. Roughly, two alternatives for speeding up computations co-exist in these resource constrained devices: parallel processing and hardware acceleration. Needles to say, multi-core devices are clearly the next step in embedded systems due to clear technological limitations on single processor frequency. Hardware accelerators are long known to be a cheaper approach for costly cryptographic functions. The authors analysis is focused on the five SHA-3 finalists which are also contrasted to the previous SHA-2 standard and to the widespread MD5. On the hardware side, the authors deploy their implementations on two platforms from Freescale: a S12X core equipped with an XGATE coprocessor and a Kinetis K60 core equipped with a crypto co-processor. These platforms differ significantly in terms of computational power, the first is based on a 16-bit Freescale proprietary architecture while the former relies on a more recent 32-bit Cortex core. The authors’ experimental results show mixed performances between the old standard and the new candidates. Some of the new candidates clearly outperform the old standard in terms of both computational speed and memory requirements while others do not. Bottom line, on the 16 bit platform BLAKE and Grøstl are the top performers while on the 32-bit platform Keccak, Blake and Skein give the best results.