Parallelization and analysis of selected numerical algorithms using OpenMP and Pluto on symmetric multiprocessing machine

PurposeIn recent years, there is a gradual shift from sequential computing to parallel computing. Nowadays, nearly all computers are of multicore processors. To exploit the available cores, parallel computing becomes necessary. It increases speed by processing huge amount of data in real time. The purpose of this paper is to parallelize a set of well-known programs using different techniques to determine best way to parallelize a program experimented.Design/methodology/approachA set of numeric algorithms are parallelized using hand parallelization using OpenMP and auto parallelization using Pluto tool.FindingsThe work discovers that few of the algorithms are well suited in auto parallelization using Pluto tool but many of the algorithms execute more efficiently using OpenMP hand parallelization.Originality/valueThe work provides an original work on parallelization using OpenMP programming paradigm and Pluto tool.

VISUALISASI PENGARUH ELEMEN PERANCANGAN CACHE PADA SYMMETRIC MULTIPROCESSORS

[Id]Cache memory merupakan salah satu pokok pembahasan penting dalam matakuliah organisasi dan arsitektur komputer. Akan tetapi, cache tidak dapat diakses dalam proses pembelajaran. Oleh karena itu, mahasiswa menghadapi kesulitan dalam memahami topik ini secara komprehensif. Makalah ini membahas tentang penggunaan simulator SMPCache dalam pembelajaran cache memory. Beberapa contoh digunakan untuk mendemostrasikan bagaimana simulator SMPCache mendukung berbagai latihan terkait dengan elemen-elemen yang menjadi pertimbangan dalam perancangan cache dan berpengaruh terhadap kinerja keseluruhan sebuah cache memory. Penilaian pedagogi dilakukan terhadap visualisasi yang disediakan oleh simulator SMPCache dalam mendukung pembelajaran cache memory pada symmetric multiprocessing. Selain itu, untuk mengetahui respon mahasiswa terhadap peranan SMPCache dalam membantu proses pembelajaran, evaluasi berupa survey pendahuluan juga dilakukan terhadap simulator tersebut. Kata kunci:Cache, SMPCache, Simulator, Organisasi dan Arsitektur Komputer[en]Cache memory is one of the important subject matter in the course of computer organization and architecture. However, the cache cannot be accessed in the learning process. Therefore, students of have difficulties in understanding this topic comprehensively. This paper focuses on the use of SMPCache simulator in learning cache memory. Some examples are used to demonstrate how SMPCache simulator supports various exercises associated with elements of cache design which affect the overall performance of a cache memory. Pedagogy assessment is conducted on the visualization provided by the simulators SMPCache in supporting the learning cache memory on a symmetric multiprocessing. In addition, to evaluate the response of students to SMPCache role in helping the learning process, an evaluation form preliminary surveys were also conducted on the simulator.Keywords:Cache, SMPCache, Simulator, Computer Organization and Architecture

Parallel instantiation of ASP programs: techniques and experiments

Answer-Set Programming (ASP) is a powerful logic-based programming language, which is enjoying increasing interest within the scientific community and (very recently) in industry. The evaluation of Answer-Set Programs is traditionally carried out in two steps. At the first step, an input program undergoes the so-called instantiation (or grounding) process, which produces a program ′ semantically equivalent to , but not containing any variable; in turn, ′ is evaluated by using a backtracking search algorithm in the second step. It is well-known that instantiation is important for the efficiency of the whole evaluation, might become a bottleneck in common situations, is crucial in several real-world applications, and is particularly relevant when huge input data have to be dealt with. At the time of this writing, the available instantiator modules are not able to exploit satisfactorily the latest hardware, featuring multi-core/multi-processor Symmetric MultiProcessing technologies. This paper presents some parallel instantiation techniques, including load-balancing and granularity control heuristics, which allow for the effective exploitation of the processing power offered by modern Symmetric MultiProcessing machines. This is confirmed by an extensive experimental analysis reported herein.