Comparison of numbers and analysis of overflow in modular arithmetic

The method of modular arithmetic consists in operating not with a number, but with its remainders after division by some integers. In the modular number system or the number system in the residual classes, a multi-bit integer in the positional number system is represented as a sequence of several positional numbers. These numbers are the remainders (residues) of dividing the original number into some modules that are mutually prime integers. The advantage of the modular representation is that it is very simple to perform addition, subtraction and multiplication operations. In parallel execution of operations, the use of modular arithmetic can significantly reduce the computation time. However, there are drawbacks to modular representation that limit its use. These include a slow conversion of numbers from modular to positional representation; the complexity of comparing numbers in modular representation; the difficulty in performing the division operation; and the difficulty of determining the presence of an overflow. The use of modular arithmetic is justified if there are fast algorithms for calculating a number from a set of remainders. This article describes a fast algorithm for converting numbers from modular representation to positional representation based on a geometric approach. The review is carried out for the case of a comparison system with two modules. It is also shown that as a result of increasing numbers in positional calculus, they successively change in a spiral on the surface of a two-dimensional torus. Based on this approach, a fast algorithm for comparing numbers and an algorithm for detecting an overflow during addition and multiplication of numbers in modular representation were developed. Consideration for the multidimensional case is possible when analyzing a multidimensional torus and studying the behavior of the turns on its surface.

High Performance Digital Filtering on Modified Multiply and Accumulate Unit in Residue Number System with Special Type of Moduli

The paper proposes the implementation of digital filtering using residue number system and the modified truncated multiply and accumulate unit. The work was carried out a theoretical analysis of digital filters using residue number system arithmetic and implemented hardware simulation on FPGA. FPGA hardware simulation results show that the use of residue number system allows to increase the frequency of digital filters up to about 4 times and hardware costs reduce up to 3 times compared to using a common positional number system. The obtained results open up the possibility for efficient hardware implementation of digital filters on modern devices (FPGA, ASIC and etc.) to solve practical problems, such as noise reduction, amplification and suppression of the frequency spectrum, interpolation, decimation, equalization and many others.

Positional Number System

In a positional number system, the numerical value of each symbol depends on its position in the sequence of digits representing the number. Any integer greater than 1 may serve as a base, and in a base b system there are b digits represented conventionally by the digits 0,1,2,..., b-1. In this paper we introduce the following four positional number systems: decimal (base-10), binary (base-2), Octal (base-8) and hexadecimal (base-16). We focus on representations of these number systems together with arithmetical operations defined on them. The study of this paper ends with the conversions of number from one system into another with examples.

THE TASK OF CHOOSING A RELIABLE PATH FOR MESSAGE TRANSMISSION IN A COMPUTER NETWORK

The article provides a calculation and comparative analysis of the reliability and productivity of computer systems in a positional binary number system and in a non-positional number system in residual classes (residual number system – RNS), for calculations and comparative we consider practical task. The main goal is to solve the task of choosing a reliable path for message transmission in a computer network. Calculation and comparative evaluation of the reliability and performance of the computer system in the RNS and the existing in the positional binary number system computer system APO-221 of the product 15E1235 (automatic message switching center - ASC) when solving the basic task of the ASC – the task of choosing the transmission path of a formalized message (path selection algorithm (PSA))

Construction of Residue Number System Using Hardware Efficient Diagonal Function

The residue number system (RNS) is a non-positional number system that allows one to perform addition and multiplication operations fast and in parallel. However, because the RNS is a non-positional number system, magnitude comparison of numbers in RNS form is impossible, so a division operation and an operation of reverse conversion into a positional form containing magnitude comparison operations are impossible too. Therefore, RNS has disadvantages in that some operations in RNS, such as reverse conversion into positional form, magnitude comparison, and division of numbers are problematic. One of the approaches to solve this problem is using the diagonal function (DF). In this paper, we propose a method of RNS construction with a convenient form of DF, which leads to the calculations modulo 2 n , 2 n − 1 or 2 n + 1 and allows us to design efficient hardware implementations. We constructed a hardware simulation of magnitude comparison and reverse conversion into a positional form using RNS with different moduli sets constructed by our proposed method, and used different approaches to perform magnitude comparison and reverse conversion: DF, Chinese remainder theorem (CRT) and CRT with fractional values (CRTf). Hardware modeling was performed on Xilinx Artix 7 xc7a200tfbg484-2 in Vivado 2016.3 and the strategy of synthesis was highly area optimized. The hardware simulation of magnitude comparison shows that, for three moduli, the proposed method allows us to reduce hardware resources by 5.98–49.72% in comparison with known methods. For the four moduli, the proposed method reduces delay by 4.92–21.95% and hardware costs by twice as much by comparison to known methods. A comparison of simulation results from the proposed moduli sets and balanced moduli sets shows that the use of these proposed moduli sets allows up to twice the reduction in circuit delay, although, in several cases, it requires more hardware resources than balanced moduli sets.

Unitary representations of wavelet groups and encoding of iterated function systems in solenoids

For points indreal dimensions, we introduce a geometry for general digit sets. We introduce a positional number system where the basis for our representation is a fixedd by dmatrix over ℤ. Our starting point is a given pair (A,𝒟) with the matrixAassumed expansive, and 𝒟 a chosen complete digit set, i.e., in bijective correspondence with the points in ℤd/ATℤd. We give an explicit geometric representation and encoding with infinite words in letters from 𝒟. We show that the attractorX(AT,𝒟) for an affine Iterated Function System (IFS) based on (A,𝒟) is a set of fractions for our digital representation of points in ℝd. Moreover our positional ‘number representation’ is spelled out in the form of an explicit IFS-encoding of a compact solenoid 𝒮Aassociated with the pair (A,𝒟). The intricate part (Theorem 6.15) is played by the cycles in ℤdfor the initial (A,𝒟)-IFS. Using these cycles we are able to write down formulas for the two maps which do the encoding as well as the decoding in our positional 𝒟-representation. We show how some wavelet representations can be realized on the solenoid, and on symbolic spaces.