A Genetic algorithm for the optimal design of a multistage amplifier

<span lang="EN-US">The optimal sizing of analog circuits is one of the most complicated processes, because of the number of variables taken into, to the number of required objectives to be optimized and to the constraint functions restrictions. The aim is to automate this activity in order to accelerate the circuits design and sizing. In this paper, we deal with the optimization of the three stage bipolar transistor amplifier performances namely the voltage gain (A_V), the input impedance (Z_IN), the output impedance (Z_OUT), the power consumption (P) and the low and the high cutoff frequency (F_L,F_H), through the Genetic Algorithm (GA). The presented optimization problem is of multi-dimensional parameters, and the trade-off of all parameters. In fact, the passive components (Resistors and Capacitors) are selected from manufactured constant values (E12, E24, E48, E96, E192) for the purpose of reduce the cost of design; also, the intrinsic parameters of transistors (hybrid parameters and the junction capacitances) are considered variables in order not to be limited in design. SPICE simulation is used to validate the obtained result/performances.</span>

Particle Swarm Optimization Design of Low-Power Multistage Amplifier using gm/ID Methodology

A design flow using the [Formula: see text]/[Formula: see text] methodology with the adaptive particle swarm optimization (PSO) algorithm is proposed for the modern analog circuit in this paper. For the advanced CMOS process, [Formula: see text]/[Formula: see text] methodology is suitable to the long channel and short channel design in all transistor operation regions. Different from the classical PSO algorithm, the adaptive PSO algorithm features the better search efficiency and faster convergence speed over the global search. Two amplifiers were designed and implemented in a standard 0.11[Formula: see text][Formula: see text]m CMOS process using MATLAB and HSPICE. Using the thermal noise coefficient [Formula: see text] and the corner frequency [Formula: see text], this paper explored the noise design budget of low-power multistage amplifier in different saturation modes. Detailed optimization of the objective function and constraints are classified into the mono-objective case and the multi-objective case. The total running times of simulations are 5649 s and 6813 s while the errors are less than 9% and 10%, respectively. Compared with CODE, GA[Formula: see text]PF and DE[Formula: see text]PF algorithms, it can save more running time and improve the accuracy of the design. Moreover, it provides more design freedom for the trade-off among gain, the gain-bandwidth (GBW) product, noise and the phase margin under worst cases without extra tweaking. Not only can the methodology work in the 0.18[Formula: see text][Formula: see text]m CMOS process, but also be migrated to the 0.11[Formula: see text][Formula: see text]m CMOS process, even in the nanometer analog circuit.