Multiprocessor Scheduling of Sensor Transactions for Real-Time Data Quality Maintenance

In cyber-physical systems, sensor transactions should be effectively scheduled to maintain the temporal validity of real-time data objects. Previous studies on sensor transaction scheduling mainly focus on uniprocessor systems. In this paper, we study the problem of data quality-based scheduling of sensor transactions on multiprocessor platforms. The data quality is defined to describe the validity degree of real-time data objects. Two methods, named the Partitioned Scheduling for Quality Maximization (P-QM) and the improved P-QM scheduling (IP-QM), are proposed. P-QM maximizes the data quality by judiciously determining the preallocated computation time of each sensor transaction and assigns the transactions to different processors. IP-QM improves the data quality obtained from P-QM by adaptively executing transaction instances on each processor based on the current status of the system. It is demonstrated through experiments that IP-QM can provide higher data quality than P-QM under different system workloads.

An Evolutionary Approach for the Hierarchical Scheduling of Safety- and Security-Critical Multicore Architectures

The aerospace and defense industry is facing an end-of-life production issue with legacy embedded uniprocessor systems. Most, if not all, embedded processor manufacturers have already moved towards system-on-a-chip multicore architectures. Current scheduling arrangements do not consider schedules related to safety and security. The methods are also inefficient because they arbitrarily assign larger-than-necessary windows of execution. This research creates a hierarchical scheduling framework as a model for real-time multicore systems to integrate the scheduling for safe and secure systems. This provides a more efficient approach which automates the migration of embedded systems’ real-time software tasks to multicore architectures. A novel genetic algorithm with a unique objective function and encoding scheme was created and compared to classical bin-packing algorithms. The simulation results show the genetic algorithm had 1.8–2.5 times less error (a 56–71% difference), outperforming its counterparts in uniformity in utilization. This research provides an efficient, automated method for commercial, private and defense industries to use a genetic algorithm to create a feasible two-level hierarchical schedule for real-time embedded multicore systems that address safety and security constraints.

Analysis on Scheduling Algorithms of Real-Time Hybrid Tasks

In real-time systems, periodic tasks and aperiodic tasks exist simultaneously. In a uniprocessor system, mainly there are Deferrable Server algorithm (DS) [1], Slack Stealing algorithm (SSA) [2] and their extended version for software/hardware hybrid real-time task scheduling. DS algorithm sets a high priority periodic task server to provide services for aperiodic tasks, while SSA algorithm computes tasks unoccupied time offline, and then schedule aperiodic tasks during the unoccupied period. The two algorithms are both proposed for soft real-time tasks, reducing the response time of the real-time tasks, but cannot guarantee that these aperiodic real-time tasks received can meet deadlines. In this paper, through combination of DS algorithm and EDF (Earliest Deadline First) algorithm [6], a new algorithm called DS-EDF is introduced, which can scheduling hard real-time aperiodic tasks on the DS server. This algorithm is not only suitable for uniprocessor systems, but also has the ability to extend to multiprocessor systems.

Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration

Due to the ever-growing requirements in high performance data computation, multiprocessor systems have been proposed to solve the bottlenecks in uniprocessor systems. Developing efficient multiprocessor systems requires effective exploration of design choices like application scheduling, mapping, and architecture design. Also, fault tolerance in multiprocessors needs to be addressed. With the advent of nanometer-process technology for chip manufacturing, realization of multiprocessors on SoC (MpSoC) is an active field of research. Developing efficient low power, fault-tolerant task scheduling, and mapping techniques for MpSoCs require optimized algorithms that consider the various scenarios inherent in multiprocessor environments. Therefore there exists a need to develop a simulation framework to explore and evaluate new algorithms on multiprocessor systems. This work proposes a modular framework for the exploration and evaluation of various design algorithms for MpSoC system. This work also proposes new multiprocessor task scheduling and mapping algorithms for MpSoCs. These algorithms are evaluated using the developed simulation framework. The paper also proposes a dynamic fault-tolerant (FT) scheduling and mapping algorithm for robust application processing. The proposed algorithms consider optimizing the power as one of the design constraints. The framework for a heterogeneous multiprocessor simulation was developed using SystemC/C++ language. Various design variations were implemented and evaluated using standard task graphs. Performance evaluation metrics are evaluated and discussed for various design scenarios.