Algorithms for Reconfiguring NoC-Based Fault-Tolerant Multiprocessor Arrays

This paper investigates the techniques to construct high-quality target processor array (fault-free logical subarray) from a physical array with faulty processing elements (PEs), where a fixed number of spare PEs are pre-integrated that can be used to replace the faulty ones when necessary. A reconfiguration algorithm is successfully developed based on our proposed novel shifting operations that can efficiently select proper spare PEs to replace the faulty ones. Then, the initial target array is further refined by a carefully designed tabu search algorithm. We also consider the problem of constructing a fault-free subarray with given size, instead of the original size, which is often required in energy-efficient MPSoC design. We propose two efficient heuristic algorithms to construct target arrays of given sizes leveraging a sliding window on the physical array. Simulation results show that the improvements of the proposed algorithms over the state of the art are [Formula: see text] and [Formula: see text], in terms of congestion factor and distance factor, respectively, for the case that all faulty PEs can be replaced using the spare ones. For the case of finding [Formula: see text] target array on [Formula: see text] host array, the proposed heuristic algorithm saves the running time up to [Formula: see text] while the solution quality keeps nearly unchanged, in comparison with the baseline algorithms.

Does seeing gesture lighten or increase the load?

We examined the cognitive resources involved in processing speech with gesture compared to the same speech without gesture across four studies using a dual-task paradigm. Participants viewed videos of a woman describing spatial arrays either with gesture or without. They then attempted to choose the target array from among four choices. Participants’ cognitive load was measured as they completed this comprehension task by measuring how well they could remember the location and identity of digits in a secondary task. We found that addressees experience additional visuospatial load when processing gestures compared to speech alone, and that the load primarily comes when addressees attempt to use their memory of the descriptions with gesture to choose the target array. However, this cost only occurs when gestures about horizontal spatial relations (i.e., left and right) are produced from the speaker’s egocentric perspective.

Response of supraoculomotor area neurons during combined saccade-vergence movements

Combined saccade-vergence movements allow humans and other primates to align their eyes with objects of interest in three-dimensions. In the absence of saccades, vergence movements are typically slow, symmetrical movements of the two eyes in opposite directions. However, combined saccade-vergence movements produce vergence velocities that exceed values observed during vergence alone. This phenomenon is often called “vergence enhancement”, or “saccade-facilitated vergence,” though it is important to consider that rapid vergence changes, known as “vergence transients,” are also observed during conjugate saccades. We developed a visual target array that allows monkeys to make saccades in all directions between targets spaced at distances that correspond to ~1° intervals of vergence angle relative to the monkey. We recorded the activity of vergence-sensitive neurons in the supra-oculomotor area (SOA), located dorsal and lateral to the oculomotor nucleus while monkeys made saccades with vergence amplitudes ranging from 0 to 10°. The primary focus of this study was to test the hypothesis that neurons in the SOA fire a high frequency burst of spikes during saccades that could generate the enhanced vergence. We found that individual neurons encode vergence velocity during both saccadic and non-saccadic vergence, yet firing rates were insufficient to produce the observed enhancement of vergence velocity. Our results are consistent with the hypothesis that slow vergence changes are encoded by the SOA while fast vergence movements require an additional contribution from the saccadic system. NEW & NOTEWORTHY Research into combined saccade-vergence movements has so far focused on exploring the saccadic neural circuitry, leading to diverging hypotheses regarding the role of the vergence system in this behavior. In this study, we report the first quantitative analysis of the discharge of individual neurons that encode vergence velocity in the monkey brain stem during combined saccade-vergence movements.

Tight Upper Bound for Accelerating Reconfiguration of VLSI Arrays

Reconfiguring a very large scale integration (VLSI) array with faults is to construct a maximum logical sub-array (target array) without faults. A large target array implies a good harvest of the corresponding reconfiguration algorithm. Thus, a tight upper bound of the harvest can be directly used to evaluate the performance of the reconfiguration algorithm. This paper presents a new approach to calculate the upper bound of the harvest for the VLSI arrays with clustered faults. The latest upper bound is successfully reduced and the proposed technique to calculate the upper bound is bound into a reconfiguration algorithm cited in this paper. Simulation results show that the upper bound is reduced up to 20% on 256 × 256 array with clustered faults, and the corresponding reconfiguration process is significantly accelerated over 30%, without loss of harvest.

On the contributions of vision and proprioception to the representation of hand-near targets

Performance is often improved when targets are presented in space near the hands rather than far from the hands. Performance in hand-near space may be improved because participants can use proprioception from the nearby limb and hand to provide a narrower and more resolute frame of reference. An equally compelling alternative is that targets appearing near the hand fall within the receptive fields of visual-tactile bimodal cells, recruiting them to assist in the visual representation of targets that appear near but not far from the hand. We distinguished between these two alternatives by capitalizing on research showing that vision and proprioception have differential effects on the precision of target representation (van Beers RJ, Sittig AC, Denier van der Gon JJ. Exp Brain Res 122: 367–377, 1998). Participants performed an in-to-center reaching task to an array of central target locations with their right hand, while their left hand rested near (beneath) or far from the target array. Reaching end-point accuracy, variability, time, and speed were assessed. We predicted that if proprioception contributes to the representation of hand-near targets, then error variability in depth will be smaller in the hand-near condition than in the hand-far condition. By contrast, if vision contributes to the representation of hand-near targets, then error variability along the lateral dimension will be smaller in the hand-near than in the hand-far condition. Our results showed that the placement of the hand near the targets reduced end-point error variability along the lateral dimension only. The results suggest that hand-near targets are represented with greater visual resolution than far targets.

CONSTRUCTING LOW-TEMPERATURE SUB-ARRAYS ON RECONFIGURABLE VLSI ARRAYS

Increasing temperatures of the processing elements (PEs) on VLSI may threaten the reliability and performance of a hard real-time system. This paper presents a temperature-aware algorithm to reconfigure two-dimensional VLSI arrays in the presence of faulty PEs. Based on dynamic programming, the proposed algorithm constructs each logical column with the lowest temperature for a cool target array on a given processor array. In addition, the lower bound of the temperatures of the cool target array has been established. Simulation results show that the temperatures of target array are reduced without loss of harvest in comparison to the state-of-the-art. Moreover, the produced peak temperature of cool target array is pretty close to the lower bound.