Implementation Features of an Analog Multiplier Based on 5529 Series Structured ASIC

During the analog signals processing one of the key factors is the reduction of power consumption with high accuracy of signal processing. One way of solving this problem is the implementation of analog IP-blocks. PLLs, AGC, modulators often include the analog signal multipliers. In the paper, the principle of quadratic function cell operation has been described in detail. The analog signal multiplier has been constructed on the basis of the difference of squares arithmetic formula and the considered cell of the quadratic current function. On the basis of the elements of 5529 series structured ASIC, the analog signal multiplier has been simulated and its accuracy has been assessed. The resulting analog complex functional IP-block for signal multiplication is a part of the development strategy for 5529 series structured ASIC library.