Single-Phase 13-Level Power Conditioning System for Peak Power Reduction of a High-Speed Railway Substation

: The control and operation of a single-phase 13-level power conditioning system (PCS) for peak power reduction of a high-speed railway substation (HSRS) are proposed. This PCS is a single-phase 3100 V, 2 MVA 13-level H-bridge multi-level inverter structure. It has excellent power quality. It is easy to serialize by voltage. In addition, the DC bus power of each cell inverter is supplied by lithium-ion batteries. The generalized reduction gradient optimization algorithm based on past load pattern is applied to the power management system for peak power reduction of HSRS. The phase detector and power controller for the control of a single-phase PCS based on virtually coordinated axes using an all-pass filter are expected to be robust to external disturbances with fast response characteristics. This study also proposes an adapted select switch (ASS) method that can change the switching depending on the operation state of PCS and the state of charge (SOC) of the battery to minimize battery imbalance by controlling each cell inverter of the H-bridge. The validity of the proposed system was confirmed by PSiM simulation and experiments using a demonstration system of 6 MW PCS and 2.68 MWh batteries at one of Gyeongbu high-speed line substations in Korea.

Dynamic Energy Reduction in TCAM Match-Line Sensing Using Charge-Sharing and Positive Feedback

Network routers use ternary content addressable memory (TCAM) for high-speed table look-up. A match-line (ML) sensing scheme for TCAM combining charge-sharing and positive feedback is presented. The objective is to simplify the ML sense amplifier (MLSA) of existing charge-sharing scheme while reducing ML energy consumption during look-up. The look-up has been performed in two steps. In the first step, a segment of each TCAM word is compared with the search key to detect large percentage of the mismatched words. The detected mismatched words are deactivated in the second step to reduce energy consumption. In the second step, the charge stored in a matched ML first segment is shared with second ML segment. Use of positive feedback in this step makes the MLSA circuit simple. Post-layout simulations implemented using 180[Formula: see text]nm 1.8[Formula: see text]V CMOS logic have been performed. In addition to lower scheme complexity and 16.5% reduction in circuit area, the proposed scheme provides dynamic energy saving up to 5.5% and peak power reduction of 52% compared to existing state-of-the-art charge-sharing technique.