Video Compression Based on FPGA Using SIMD Architecture

Recently, video files and images have became the dominant media material for transmitting or storing across different applications that are used by different people. So, there was a serious need to find more effective and efficient video compression techniques to reduce the large size of such multimedia files. This paper proposes SIMD based FPGA lossless JPEG video compression system with the facility of scalability. Generally, the proposed system consists of a software side and a hardware side. The digital video file is prepared to be processed by the hardware side frame by frame on the software side. The hardware side is proposed to consist of two main processing circuits, which are the prediction circuit for calculating the predicted value of each pixel in the certain frame and the encoding circuit that was represented by a modified RLE (Run-Length-Encoder) to encode the result obtained through subtracting the predicted value from the real value for each pixel to produce the final compressed video file. The compression ratio obtained for the proposed system is equal to 1.7493. The throughput improvement for the two and four processing units basing on SIMD architecture was 100 MP/s and 200 MP/s, respectively. The clock results showed that the number of clocks required had become 50% and 25% when using two processing units and four processing units, respectively, from the number of clocks using single processing units. Index Terms— Video Compression, Lossless JPEG, RLE, FPGA.

Method of parallelization of loops for grid calculation problems on GPU accelerators

The formal parallelizing transformation of a nest of calculation loop for SIMD architecture devices, particularly for graphics processing units applying CUDA technology and heterogeneous clusters is developed. Procedure of transition from sequential to parallel algorithm is described and illustrated. Serialization of data is applied to optimize processing of large volumes of data. The advantage of the suggested method is its applicability for transformation of data which volumes exceed the memory of operating device. The experiment is conducted to demonstrate feasibility of the proposed approach. Technique presented in the provides the basis for further practical implementation of the automated system for parallelizing of nested loops.