Minimization of SIDELOBE Attenuation and Power of a Fir Low Pass Filter using FRFT and CSD Algorithm

For digital signal processing, communication systems and VLSI design architectures, an efficient FIR filter is required to eliminate the noise signals. To design an efficient FIR filter, the minimization of two parameters is required such as side lobe attenuation and power. These two parameters can be achieved by designing a FIR filter with the help of Fractional Fourier Transform (FrFT) and Canonical Signed digit (CSD) algorithm. In this work, Finite Impulse Response (FIR) low pass filter is designed by using both FrFT and ordinary Fourier Transform (FT) methods and their frequency responses are compared in terms of side lobe attenuation (SLA). After comparison of both methods, the better results are obtained for an FrFT based design of FIR low pass filter. Apart from this, the FrFT based design of FIR low pass filter is realized in direct form architecture and implemented in VLSI. Further, the Canonical Signed digit (CSD) algorithm is applied for the multiplication process in the architecture implementation to minimize the power consumption. Moreover, frequency response of FIR low pass filter is obtained by using MATLAB software and simulation and synthesis results are obtained by using Xilinx 13.1 ISE.

Another Implementation of Efficient Recoding Circuit for Signed Digit to Residue Canonical Signed Digit on Modulo 2n-1

In this paper, we propose an efficient SD-to-RCSD recoding circuit structure on modulo. This structure is based on the parallel prefix addition circuit, that is, a carry for each digits is precalculated in parallel.

A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis

The fast Fourier transform (FFT) is the most prevalent algorithm for the spectral analysis of acoustic emission signals acquired at ultra-high sampling rates to monitor the condition of rotary machines. The complexity and cost of the associated hardware limit the use of FFT in real-time applications. In this paper, an efficient hardware architecture for FFT implementation is proposed based on the radix-2 decimation in frequency algorithm (R2DIF) and a feedback pipelined technique (FB) that allows effective sharing of storage between the input and output data at each stage of the FFT process via shift registers. The proposed design uses an optimal hybrid rotation scheme by combining the modified coordinate rotation digital computer (m-CORDIC) algorithm and a binary encoding technique based on canonical signed digit (CSD) for replacing the complex multipliers in FFT. The m-CORDIC algorithm, with an adaptive iterative monitoring process, improves the convergence of computation, whereas the CSD algorithm optimizes the multiplication of constants using a simple shift-add method. Therefore, the proposed design does not require the large memory typically entailed by existing designs to carry out twiddle factor multiplication in large-point FFT implementations, thereby reducing its area on the chip. Moreover, the proposed pipelined FFT processor uses only distributed logic resources and does not require expensive dedicated functional blocks. Experimental results show that the proposed design outperforms existing state-of-the-art approaches in speed by about 49% and in resource utilization by around 51%, while delivering the same accuracy and utilizing less chip area.