branch target buffer Latest Research Papers

PDede: Partitioned, Deduplicated, Delta Branch Target Buffer

10.1145/3466752.3480046 ◽

2021 ◽

Author(s):

Niranjan K Soundararajan ◽

Peter Braun ◽

Tanvir Ahmed Khan ◽

Baris Kasikci ◽

Heiner Litz ◽

...

Keyword(s):

Branch Target Buffer ◽

Delta Branch

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Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer

2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA) ◽

10.1109/isca.2018.00050 ◽

2018 ◽

Cited By ~ 3

Author(s):

Samira Mirbagher Ajorpaz ◽

Elba Garza ◽

Sangam Jindal ◽

Daniel A. Jimenez

Keyword(s):

Instruction Cache ◽

Branch Target Buffer

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Leakage-Aware Speculative Branch Target Buffer

Journal of Low Power Electronics ◽

10.1166/jolpe.2012.1218 ◽

2012 ◽

Vol 8 (5) ◽

pp. 595-603

Author(s):

Saman Khoshbakht ◽

Amirali Baniasadi

Keyword(s):

Branch Target Buffer

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Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques

Journal of Low Power Electronics ◽

10.1166/jolpe.2012.1219 ◽

2012 ◽

Vol 8 (5) ◽

pp. 604-623

Author(s):

Sumanta Pyne ◽

Ajit Pal

Keyword(s):

Energy Reduction ◽

Branch Target Buffer ◽

Translation Techniques

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A SBST strategy to test microprocessors' Branch Target Buffer

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) ◽

10.1109/ddecs.2012.6219079 ◽

2012 ◽

Cited By ~ 6

Author(s):

P. Bernardi ◽

L. Ciganda ◽

M. Grosso ◽

E. Sanchez ◽

M. Sonza Reorda

Keyword(s):

Branch Target Buffer

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Energy Saving of Value Prediction by Expanding Branch Target Buffer

IEEJ Transactions on Electronics Information and Systems ◽

10.1541/ieejeiss.132.1706 ◽

2012 ◽

Vol 132 (10) ◽

pp. 1706-1718

Author(s):

Yoshio Shimomura ◽

Ryotaro Kobayashi

Keyword(s):

Energy Saving ◽

Value Prediction ◽

Branch Target Buffer

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Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures

IET Computers & Digital Techniques ◽

10.1049/iet-cdt.2010.0102 ◽

2012 ◽

Vol 6 (1) ◽

pp. 50 ◽

Cited By ~ 1

Author(s):

S. Wang ◽

J. Hu ◽

S.G. Ziavras

Keyword(s):

High Performance ◽

Low Energy ◽

Branch Target Buffer

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Branch target buffer design for embedded processors

Microprocessors and Microsystems ◽

10.1016/j.micpro.2010.04.005 ◽

2010 ◽

Vol 34 (6) ◽

pp. 215-227

Author(s):

Nadav Levison ◽

Shlomo Weiss

Keyword(s):

Embedded Processors ◽

Branch Target Buffer ◽

Buffer Design

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Low Power Branch Target Buffer Design Based on Hopping Access

Journal of Computer-Aided Design & Computer Graphics ◽

10.3724/sp.j.1089.2010.10629 ◽

2010 ◽

Vol 22 (4) ◽

pp. 695-702 ◽

Cited By ~ 2

Author(s):

Mingyan Yu ◽

Xiangjian Zhang ◽

Bing Yang

Keyword(s):

Low Power ◽

Branch Target Buffer ◽

Buffer Design

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Countermeasures Against Branch Target Buffer Attacks

Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 2007) ◽

10.1109/fdtc.2007.4318987 ◽

2007 ◽

Author(s):

Giovanni Agosta ◽

Luca Breveglieri ◽

Gerardo Pelosi ◽

Israel Koren

Keyword(s):

Branch Target Buffer

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branch target buffer
Recently Published Documents

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PDede: Partitioned, Deduplicated, Delta Branch Target Buffer

Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer

Leakage-Aware Speculative Branch Target Buffer

Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques

A SBST strategy to test microprocessors' Branch Target Buffer

Energy Saving of Value Prediction by Expanding Branch Target Buffer

Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures

Branch target buffer design for embedded processors

Low Power Branch Target Buffer Design Based on Hopping Access

Countermeasures Against Branch Target Buffer Attacks

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branch target bufferRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

PDede: Partitioned, Deduplicated, Delta Branch Target Buffer

Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer

Leakage-Aware Speculative Branch Target Buffer

Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques

A SBST strategy to test microprocessors' Branch Target Buffer

Energy Saving of Value Prediction by Expanding Branch Target Buffer

Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures

Branch target buffer design for embedded processors

Low Power Branch Target Buffer Design Based on Hopping Access

Countermeasures Against Branch Target Buffer Attacks

branch target buffer
Recently Published Documents