Indium-Based Micro-Bump Array Fabrication Technology with Added Pre-Reflow Wet Etching and Annealing

Indium-based micro-bump arrays, among other things, are used for the bonding of infrared photodetectors and focal plane arrays. In this paper, several aspects of the fabrication technology of micrometer-sized indium bumps with a smooth surface morphology were investigated. The thermal evaporation of indium has been optimized to achieve ~8 μm-thick layers with a small surface roughness of Ra = 11 nm, indicating a high packing density of atoms. This ensures bump uniformity across the sample, as well as prevents oxidation inside the In columns prior to the reflow. A series of experiments to optimize indium bump fabrication technology, including a shear test of single columns, is described. A reliable, repeatable, simple, and quick approach was developed with the pre-etching of indium columns in a 10% HCl solution preceded by annealing at 120 °C in N2.

Managing Voids in Underfill Process with 5-micron Gap Under Large Die

Microelectronic packaging is continuously becoming smaller and denser, thus allowing for more functionalities and smaller devices including portable products. Flip-chip among other technologies continues to enable such trends. In fact denser arrays such as copper pillars or micro bumps of various metallurgies seem to be the technology of choice for the near future electronic interconnect. A technique is reviewed for successfully underfilling a 3cm2 Indium Phosphide flip-chip die mounted on a silicon substrate with 5 microns gap and large number of I/O (about 0.3 million indium bumps) connected in daisy chains. The method that resulted in a void-free underfill consisted of line dispensing along one side of the die such that the flow of the capillary fluid was normal to the direction of the daisy chains. For dot-dispense, substrate surface treatment and more careful design of dispense sequence helped to reduce voids. This study was compared to a manual dot-dispense technique that was unable to meet production throughput requirement, accuracy, repeatability and void-free. Achievement of void-free automated underfill into a 5-micron gap with complex features underneath a large flip chips will encourage today's microelectronic packaging industry to meet the challenges of smaller and denser components.