Design techniques for passive wireless microsystems

The unique advantage of harvesting power wirelessly has evolved passive wireless microsystems to a fast-growing high-impact technology. In this dissertation, several new design techniques are proposed for the increasingly stringent requirements of passive wireless microsystems. The absence of on-board batteries imposes ultralow power consumption of passive wireless microsystems. Recent research reveals that multi-voltage systems-on-a-chip dramatically reduce power consumption such that power-efficient on-chip voltage level shifters are critically needed. This dissertation proposes a novel set of voltage level shifters built upon diode-based clamper-rectifier configurations. The voltage level shifters are passively powered by incoming signals with no static current consumption and are able to shift the incoming signals bidirectionally to suit the different voltage domains. The shifting steps could be continuous and are not bounded by the discrete transistor thresholds and power rails. A second bottleneck of passive wireless microsystems is the wireless power-harvesting efficiency that limits the wireless communication distance and the on-chip circuitry complexity and functionality. This dissertation proposes a transformer-based impedance matching network that greatly improves the power transfer efficiency from the receiving antenna to the on-chip circuit loads. The transformer is also capable of automatically calibrating its input impedance to match to the antenna impedance by a novel low-power varactor current tuning technique. In passive wireless microsystems, data modulation scheme largely determines the power transmission efficiency and data communication speed. Exploiting the constant carrier envelop of FSK modulation, this dissertation proposes a dual-tank architecture for FSK receivers in passive wireless microsystems. The dual receiving tanks significantly improves the power conversion efficiency of on-chip AC-to-DC voltage multipliers by providing high-quality-factor resonating tank voltages at each of the alternating FSK carriers. High data transmission rate is also achieved by exploring the dual tanks in an all-digital and a voltage-level shifting FSK demodulators.

Design techniques for passive wireless microsystems

The unique advantage of harvesting power wirelessly has evolved passive wireless microsystems to a fast-growing high-impact technology. In this dissertation, several new design techniques are proposed for the increasingly stringent requirements of passive wireless microsystems. The absence of on-board batteries imposes ultralow power consumption of passive wireless microsystems. Recent research reveals that multi-voltage systems-on-a-chip dramatically reduce power consumption such that power-efficient on-chip voltage level shifters are critically needed. This dissertation proposes a novel set of voltage level shifters built upon diode-based clamper-rectifier configurations. The voltage level shifters are passively powered by incoming signals with no static current consumption and are able to shift the incoming signals bidirectionally to suit the different voltage domains. The shifting steps could be continuous and are not bounded by the discrete transistor thresholds and power rails. A second bottleneck of passive wireless microsystems is the wireless power-harvesting efficiency that limits the wireless communication distance and the on-chip circuitry complexity and functionality. This dissertation proposes a transformer-based impedance matching network that greatly improves the power transfer efficiency from the receiving antenna to the on-chip circuit loads. The transformer is also capable of automatically calibrating its input impedance to match to the antenna impedance by a novel low-power varactor current tuning technique. In passive wireless microsystems, data modulation scheme largely determines the power transmission efficiency and data communication speed. Exploiting the constant carrier envelop of FSK modulation, this dissertation proposes a dual-tank architecture for FSK receivers in passive wireless microsystems. The dual receiving tanks significantly improves the power conversion efficiency of on-chip AC-to-DC voltage multipliers by providing high-quality-factor resonating tank voltages at each of the alternating FSK carriers. High data transmission rate is also achieved by exploring the dual tanks in an all-digital and a voltage-level shifting FSK demodulators.

Radio-Frequency Power Harvest And Remote Clock Frequency Calibration Of Passive Wireless Microsystems

This thesis deals with radio frequency power harvest and remote calibration of system clock of passive wireless microsystems. The proposed method of RF power harvesting utilizes a step-up transformer inserted between the antenna and voltage multiplier of passive wireless microsystems to perform both impedance transformation for power matching and voltage amplification prior to rectification. The series resistance of the primary winding is minimized while in the secondary winding, the shunt capacitive losses are minimized. The detailed analysis of the proposed method and simulation results from Spectre of Cadence Design Systems are presented. The proposed power-matching and gain -boosting network, together with voltage multipliers, has been implemented in TSMC-0.18..m 1.8V6-meatl CMOS technology with thick metal options. For the purpose of comparison, a LC power-matching and gain-boosting network with the identical voltage multiplier has also been implemented on the same chip. Measurement results demonstrate that the proposed transformer power-matching and gain-boosting technique greatly improves the power sensitivity and efficiency as compared with widely used LC matching approaches. The proposed calibration method adjusts the frequency of the local oscillator of passive UHF wireless transponders to the desired values using an injection-locked phase-locked loop (IL-PLL). A new relaxation oscillator whose oscillation frequency is less sensitive to supply voltage fluctuation is also proposed. The power consumption of the proposed IL-PLL is minimized by operating it the sub-threshold. A detailed analysis of non-harmonic injection locking of relaxation oscillators including locking and pulling dynamics is presented. A new integrating feedback is proposed to increase the lock range and hold the locked frequency in the absence of the injection signal. The proposed ILL-PLL has been fabricated in TSMC-0.18.

Radio-Frequency Power Harvest And Remote Clock Frequency Calibration Of Passive Wireless Microsystems

This thesis deals with radio frequency power harvest and remote calibration of system clock of passive wireless microsystems. The proposed method of RF power harvesting utilizes a step-up transformer inserted between the antenna and voltage multiplier of passive wireless microsystems to perform both impedance transformation for power matching and voltage amplification prior to rectification. The series resistance of the primary winding is minimized while in the secondary winding, the shunt capacitive losses are minimized. The detailed analysis of the proposed method and simulation results from Spectre of Cadence Design Systems are presented. The proposed power-matching and gain -boosting network, together with voltage multipliers, has been implemented in TSMC-0.18..m 1.8V6-meatl CMOS technology with thick metal options. For the purpose of comparison, a LC power-matching and gain-boosting network with the identical voltage multiplier has also been implemented on the same chip. Measurement results demonstrate that the proposed transformer power-matching and gain-boosting technique greatly improves the power sensitivity and efficiency as compared with widely used LC matching approaches. The proposed calibration method adjusts the frequency of the local oscillator of passive UHF wireless transponders to the desired values using an injection-locked phase-locked loop (IL-PLL). A new relaxation oscillator whose oscillation frequency is less sensitive to supply voltage fluctuation is also proposed. The power consumption of the proposed IL-PLL is minimized by operating it the sub-threshold. A detailed analysis of non-harmonic injection locking of relaxation oscillators including locking and pulling dynamics is presented. A new integrating feedback is proposed to increase the lock range and hold the locked frequency in the absence of the injection signal. The proposed ILL-PLL has been fabricated in TSMC-0.18.

Frequency calibration of the system clock of passive wireless microsystems

This thesis presents a theoretical and simulated study of frequency calibration of the system clock of passive wireless microsystems. The proposed frequency calibration technique achieves ultra-low power, high fre- quency accuracy, and fast calibration of the frequency of a local oscillator in a passive wireless microsystem using a frequency-locked loop (FLL). A new integrating frequency dif- ference detector (iFDD) that senses the frequency difference between the local oscillator and a reference clock is also proposed. The iFDD is implemented using a switched-capacitor network with two integrating paths. The FLL is composed of a logic-control block for gen- eration of clock signals, the iFDD, and a relaxation voltage-controlled oscillator. A detailed analysis of the characteristics of the iFDD in the time and frequency domains is presented. The loop dynamics of the FLL is also investigated. The proposed FLL is implemented in IBM 0.13-µm, 1.2 V CMOS technology and is validated through simulations using Spectre APS.

Frequency calibration of the system clock of passive wireless microsystems

This thesis presents a theoretical and simulated study of frequency calibration of the system clock of passive wireless microsystems. The proposed frequency calibration technique achieves ultra-low power, high fre- quency accuracy, and fast calibration of the frequency of a local oscillator in a passive wireless microsystem using a frequency-locked loop (FLL). A new integrating frequency dif- ference detector (iFDD) that senses the frequency difference between the local oscillator and a reference clock is also proposed. The iFDD is implemented using a switched-capacitor network with two integrating paths. The FLL is composed of a logic-control block for gen- eration of clock signals, the iFDD, and a relaxation voltage-controlled oscillator. A detailed analysis of the characteristics of the iFDD in the time and frequency domains is presented. The loop dynamics of the FLL is also investigated. The proposed FLL is implemented in IBM 0.13-µm, 1.2 V CMOS technology and is validated through simulations using Spectre APS.