Development of Multiobjective High-Level Synthesis for FPGAs

Traditionally, the High-Level Synthesis (HLS) for Field Programmable Gate Array (FPGA) devices is a methodology that transforms a behavioral description, as the timing-independent specification, to an abstraction level that is synthesizable, like the Register Transfer Level. This process can be performed under a framework that is known as Design Space Exploration (DSE), which helps to determine the best design by addressing scheduling, allocation, and binding problems, all three of which are NP-hard problems. In this manner, and due to the increased complexity of modern digital circuit designs and concerns regarding the capacity of the FPGAs, designers are proposing novel HLS techniques capable of performing automatic optimization. HLS has several conflicting metrics or objective functions, such as delay, area, power, wire length, digital noise, reliability, and security. For this reason, it is suitable to apply Multiobjective Optimization Algorithms (MOAs), which can handle the different trade-offs among the objective functions. During the last two decades, several MOAs have been applied to solve this problem. This paper introduces a comprehensive analysis of different MOAs that are suitable to perform HLS for FPGA devices. We highlight significant aspects of MOAs, namely, optimization methods, intermediate structures where the optimizations are performed, HLS techniques that are addressed, and benchmarks and performance assessments employed for experimentation. In addition, we show the analysis of how multiple objectives are optimized currently in the algorithms and which are the objective functions that are optimized. Finally, we provide insights and suggestions to contribute to the solution of major research challenges in this area.

VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH

In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increase in hard & fast circuits, delay also increases simultaneously. That’s the reason these Carry look ahead adders (CLA) are used. The carry look ahead adder speeds up the addition by reducing the amount of time required to determine carry bits. It uses two blocks, carry generator (Gi) and carry propagator (Pi) which finds the carry bit in advance for each bit position from the nearest LSB, if the carry is 1 then that position is going to propagate a carry to next adder.

Design of Platform for Digital Electronic Technology Based on EP3C5E

A platform for digital electronic technology is presented based on FPGA, which is built by using of Cyclone III EP3C5E of ALTERA. The platform is engineered not only for a variety of digital circuit designs but also for in-system programmable design. Voter system as an example, function of design is completed by design of module and the hardware language, and the result is compared with other function modules. Furthermore, the accuracy of the running result from platform was analyzed by using design of system module. The performance test results show that the platform adequately satisfies the need of digital electronic technology and run well.