Formal Specification of RTL-Level Digital System Using Projection Temporal Logic

An approach to specify a RTL-level system using Projection Temporal Logic (PTL) is proposed in this paper. With this approach, a digital system described with Register Transfer Language can be translated into PTL formulae, and properties of the system can be specified by PTL either. Then MSVL(Modeling, Simulation and Verification Language) can be used for detecting the error of the design formally.