Design and Implementation of Synthesizable 32-bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL

This paper is delineating the design and implementation of high performance, synthesizable 32-bit pipelined Reduced Instruction Set Computer (RISC) Core. The design of the Harvard Architecture based 32-bit RISC Core involves design of 32-bit Data-path Unit, Control Unit, 32-bit Instruction Memory, 32-bit Data Memory, Register file with each register of size 32 bit. The processor is divided into Fetch, Decode, Execute and Write Back block in order to implement a four-stage pipeline. A 2*16 LCD is connected to the processor IO block to show the instruction execution sequence for demonstration in FPGA. The RISC Core is designed using Verilog HDL and VHDL and is tested in ISIM Simulator. The implementation of the processor is done in a Spartan 3E Starter Board using Xilinx ISE 14.7. All of the instructions incorporated with the processor have been tested successfully both in simulation and hardware implementation in FPGA.DOI: http://dx.doi.org/10.3126/njst.v15i1.12021 Nepal Journal of Science and TechnologyVol. 15, No.1 (2014) 81-88

Auxiliary Device for SCM and its Design Project

The experiment circuit is divided into two parts: fixed and non-fixed in a synthetical teaching experiment for SCM.The fixed part is made ​​of printed circuit board in its auxiliary device, the non-fixed part is lapped on the bread board by the experimenters .Above contents include:(1) system storage structure is non fixed, which using the jumper switch K1, the system structure may become the Princeton structure, or Harvard architecture or no RAM structure;(2) system storage capacity is non fixed, which using the jumper switch K1,K2, the chip EPROM or RAM is arbitrarily selected by experiment system according to the needs. Experiences show: this auxiliary device improves the flexibility and versatility,saves time, strengthens the experimenter’s operational ability and improves the success rate for the SCM experiment.