A Review of Techniques for Optimizing Cache Energy Efficiency

In today’s computer, there are larger sizes of the cache are using on the chip. Moreover, there is significant change has happened in the technology. Because of that change cache power efficiency has become the important issue in the processors. To solve this problem most of the researchers have proposed a different methodology to improve the cache energy efficiency. This paper review different techniques that are proposed for improving cache energy efficiency. There are different techniques discussed in this survey paper that is used to improve the cache energy at a different level of the cache. The main focus of the paper of survey is to urge the different researcher to propose different methodology so they can make the cache more efficient and energy saving.

Modeling Energy-Delay Tradeoffs in Single Base Station with Cache

With the explosive increase of mobile data traffic, the energy efficiency issue in cellular networks is a growing concern. Recently, the advantages of in-network caching in Internet have been widely investigated, for example, speeding up content distribution and improving network resource utilization. In this paper, we analyze the energy-delay tradeoff problem in the context of single base station (BS), which has a cache capacity to buffer the contents through it. Although additional power is consumed by the cache, work load of BS and network delay will be improved, which makes a tradeoff between network power consumption and delay. Simulation results reveal that, by introducing the cache in a BS, the network power and delay can be obviously reduced in different network conditions compared to the scenario without a cache. In addition, we find that a large cache size does not always mean a less network cost because of the more cache power consumption.

A Data Drivered Refresh with Multi-Bit Error-Correcting Power Optimize Method for Cache Based eDRAM

Power problem has been one of most restricting the development barriers of processor. With enhancing of computer performance, there must be large cache to hide memory latency. Large cache can be consisted on one chip based eDRAM which has high density. Unfortunately, eDRAM must be refreshed frequently to maintain data, which would increase cache power. The paper aims at refresh problem of eDRAM, and put forwards a data drivered refresh with multi-bit error-correcting power optimize method. The experimental results show that the method which we put forward can greatly reduce the refresh power of eDRAM.