Simulação analítica de espelhos de corrente utilizando associação série do transistores SOI MOSFET

This work presents an analysis of the advantages of symmetric (S-SC) and asymmetric (A-SC) self-cascode associations of nMOSFETs in relation to a single transistor (ST) SOI MOSFET by means of analytical simulations of basic analog blocks. Besides presenting the characteristics of a single transistor amplifier, current mirrors with different architectures are studied. The study and evaluation of these analog blocks were performed based on electricals characteristics obtained from SPICE circuits simulations, using ICAP/4 software. Initially, model parameters were adjusted to fit experimental data, to ensure simulated devices characteristics similar to the real ones. After these adjustments, symmetric self-cascode (association of two transistors with identical threshold voltages) and asymmetric self-cascode (association of two transistors with different threshold voltages) of SOI nMOSFETs were simulated at device level. Electrical parameters such as drain current (IDS), transconductance (gm), output conductance (gD), Early voltage (VEA), open loop gain voltage and gm/IDS ratio are presented as a function of the voltage applied to single transistor terminals and composite device (symmetric and asymmetric associations) with different dimensions. Then, the series associations and the single transistors (ST) were used in current mirrors circuits in CommonSource and single transistor in Cascode and Wilson architectures to verify the composed structure performance. It has been verified that current mirror using association S-SC present electrical behavior similar to the current mirror formed by SOI MOSFET ST, with the same channel length. It has been observed that the association A-SC features better electric performance in relation to the S-SC and ST in common-source current mirror, as well, in relation to Cascode and Wilson architectures using single transistors, in week and moderate inversion regions, due to the better output conductance and, consequently, the higher Early voltage