Técnicas para la implementación de turbo decodificadores con baja latencia

Turbo coding is a channel coding technique that increases the capacity of communications systems, especially wireless and mobile. Due to its high correction capability, this technique is used in modern wireless communication standards such as 3GPP and LTE/LTE-Advanced. One of the features of these systems is the increase in data processing capacity, where transmission rates of up to 1 Gbps are specified. However, the turbo coding technique inherently presents a limited performance as a consequence of the turbo decoding process at the reception stage. The turbo decoder presents a high operation latency mainly caused by the iterative decoding process, the interleaver and deinterleaver stage and the estimation process of the information bits. In this work, we show the techniques used to implement modern low-latency turbo decoders suitable for 3G and 4G standards.

VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes

This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital transmission chains. For example, for the Turbo decoder based on the product code DSC (21.11)² with a quantization of 5 bits and for one complete iteration, the results show the possibility of integration of our entire turbo decoder on a single chip, with lower latency at 0.23 microseconds and data rate greater than 500 Mb/s.