memory instruction
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2021 ◽  
Author(s):  
Muhammad Umair Zafar

This work investigates the dynamic energy efficiency of the parallel execution model of an FPGA and the sequential execution model of a processor, for latency-insensitive applications. We create the temporal implementations (sequential instructions) of the MCNC benchmarks to be executed on a processor that employs a 4LUT as its functional unit. This processor is ~716 times inefficient for dynamic energy than a 4LUT FPGA, mainly due to the large amount of memory (instruction/data) that is required to encode the 4LUT based instructions. The size of the memory (instruction/data) can be reduced by increasing the data-path width and the logic complexity of the ASIC-based functional units of the processor. Particularly, at 64-bit data-path width and when the (instruction/data) memory sizes are reduced to less than ~9% of their corresponding 4LUT-based instructions, the processor with ASIC-based complex functional unit can achieve higher dynamic energy efficiency than the FPGA for MCNC benchmarks.


2021 ◽  
Author(s):  
Muhammad Umair Zafar

This work investigates the dynamic energy efficiency of the parallel execution model of an FPGA and the sequential execution model of a processor, for latency-insensitive applications. We create the temporal implementations (sequential instructions) of the MCNC benchmarks to be executed on a processor that employs a 4LUT as its functional unit. This processor is ~716 times inefficient for dynamic energy than a 4LUT FPGA, mainly due to the large amount of memory (instruction/data) that is required to encode the 4LUT based instructions. The size of the memory (instruction/data) can be reduced by increasing the data-path width and the logic complexity of the ASIC-based functional units of the processor. Particularly, at 64-bit data-path width and when the (instruction/data) memory sizes are reduced to less than ~9% of their corresponding 4LUT-based instructions, the processor with ASIC-based complex functional unit can achieve higher dynamic energy efficiency than the FPGA for MCNC benchmarks.


2019 ◽  
Vol 130 ◽  
pp. 193-207 ◽  
Author(s):  
Lifeng Nai ◽  
Ramyad Hadidi ◽  
He Xiao ◽  
Hyojong Kim ◽  
Jaewoong Sim ◽  
...  
Keyword(s):  

2015 ◽  
pp. 181-215
Author(s):  
CELIA CHAZELLE
Keyword(s):  

2004 ◽  
Vol 32 (3) ◽  
pp. 199-224
Author(s):  
Daniel Ortega ◽  
Mateo Valero ◽  
Eduard Ayguadé

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