Mitigating Voltage Attacks in Multi-Tenant FPGAs

Recent research has exposed a number of security issues related to the use of FPGAs in embedded system and cloud computing environments. Circuits that deliberately waste power can be carefully crafted by a malicious cloud FPGA user and deployed to cause denial-of-service and fault injection attacks. The main defense strategy used by FPGA cloud services involves checking user-submitted designs for circuit structures that are known to aggressively consume power. Unfortunately, this approach is limited by an attacker’s ability to conceive new designs that defeat existing checkers. In this work, our contributions are twofold. We evaluate a variety of circuit power wasting techniques that typically are not flagged by design rule checks imposed by FPGA cloud computing vendors. The efficiencies of five power wasting circuits, including our new design, are evaluated in terms of power consumed per logic resource. We then show that the source of voltage attacks based on power wasters can be identified. Our monitoring approach localizes the attack and suppresses the clock signal for the target region within 21 μs, which is fast enough to stop an attack before it causes a board reset. All experiments are performed using a state-of-the-art Intel Stratix 10 FPGA.

Fast and resource-efficient Deep Neural Network on FPGA for the Phase-II Level-0 muon barrel trigger of the ATLAS experiment

The Level-0 muon trigger system of the ATLAS experiment will undergo a full upgrade for the High Luminosity LHC to stand the challenging requirements imposed by the increase in instantaneous luminosity. The upgraded trigger system will send raw hit data to off-detector processors, where trigger algorithms run on a new generation of FPGAs. To exploit the flexibility provided by the FPGA systems, ATLAS is developing novel precision deep neural network architectures based on trained ternary quantisation, optimised to run on FPGAs for efficient reconstruction and identification of muons in the ATLAS “Level-0” trigger. Physics performance in terms of efficiency and fake rates and FPGA logic resource occupancy and timing obtained with the developed algorithms are discussed.

Service ecosystem well-being: conceptualization and implications for theory and practice

Purpose This paper aims to conceptualize and characterize service ecosystems, addressing calls for research on this important and under-researched topic. Design/methodology/approach The authors draw on four meta-theoretical foundations of S-D logic – resource integration, resource density, practices and institutions – providing a new integrated conceptual framework of ecosystem well-being. They then apply this conceptualization in the context of a complex healthcare setting, exploring the characteristics of ecosystem well-being at the meso level. Findings This study provides an integrated conceptual framework to explicate the nature and structure of well-being in a complex service ecosystem; identifies six key characteristics of ecosystem well-being; illustrates service ecosystem well-being in a specific healthcare context, zooming in on the meso level of the ecosystem and noting the importance of embedding a shared worldview; provides practical guidance for managers and policy makers about how to manage complex service ecosystems in their quest for improving service outcomes; and offers an insightful research agenda. Research limitations/implications This research focuses on service ecosystems with an illustration in one healthcare context, suggesting additional studies that explore other industry contexts. Practical implications Practically, the study indicates the imperative for managing across mutually adapting levels of the ecosystem, identifying specific new practices that can improve service outcomes. Social implications Examining well-being in the context of a complex service ecosystem is critical for policymakers charged with difficult decisions about balancing the demands of different levels and actors in a systemic world. Originality/value The study is the first to conceptualize and characterize well-being in a service ecosystem, providing unique insights and identifying six specific characteristics of well-being.

Convolution Accelerator Designs Using Fast Algorithms

Convolutional neural networks (CNNs) have achieved great success in image processing. However, the heavy computational burden it imposes makes it difficult for use in embedded applications that have limited power consumption and performance. Although there are many fast convolution algorithms that can reduce the computational complexity, they increase the difficulty of practical implementation. To overcome these difficulties, this paper proposes several convolution accelerator designs using fast algorithms. The designs are based on the field programmable gate array (FPGA) and display a better balance between the digital signal processor (DSP) and the logic resource, while also requiring lower power consumption. The implementation results show that the power consumption of the accelerator design based on the Strassen–Winograd algorithm is 21.3% less than that of conventional accelerators.

High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing

Parallel hardware designed for image processing promotes vision-guided intelligent applications. With the advantages of high-throughput and low-latency, streaming architecture on FPGA is especially attractive to real-time image processing. Notably, many real-world applications, such as region of interest (ROI) detection, demand the ability to process images continuously at different sizes and resolutions in hardware without interruptions. FPGA is especially suitable for implementation of such flexible streaming architecture, but most existing solutions require run-time reconfiguration, and hence cannot achieve seamless image size-switching. In this paper, we propose a dynamically-programmable buffer architecture (D-SWIM) based on the Stream-Windowing Interleaved Memory (SWIM) architecture to realize image processing on FPGA for image streams at arbitrary sizes defined at run time. D-SWIM redefines the way that on-chip memory is organized and controlled, and the hardware adapts to arbitrary image size with sub-100 ns delay that ensures minimum interruptions to the image processing at a high frame rate. Compared to the prior SWIM buffer for high-throughput scenarios, D-SWIM achieved dynamic programmability with only a slight overhead on logic resource usage, but saved up to 56 % of the BRAM resource. The D-SWIM buffer achieves a max operating frequency of 329.5 MHz and reduction in power consumption by 45.7 % comparing with the SWIM scheme. Real-world image processing applications, such as 2D-Convolution and the Harris Corner Detector, have also been used to evaluate D-SWIM’s performance, where a pixel throughput of 4.5 Giga Pixel/s and 4.2 Giga Pixel/s were achieved respectively in each case. Compared to the implementation with prior streaming frameworks, the D-SWIM-based design not only realizes seamless image size-switching, but also improves hardware efficiency up to 30 × .

RP-Ring: A Heterogeneous Multi-FPGA Accelerator

To reduce the cost of designing new specialized FPGA boards as direct-summation MOND (Modified Newtonian Dynamics) simulator, we propose a new heterogeneous architecture with existing FPGA boards, which is called RP-ring (reconfigurable processor ring). This design can be expanded conveniently with any available FPGA board and only requires quite low communication bandwidth between FPGA boards. The communication protocol is simple and can be implemented with limited hardware/software resources. In order to avoid overall performance loss caused by the slowest board, we build a mathematical model to decompose workload among FPGAs. The dividing of workload is based on the logic resource, memory access bandwidth, and communication bandwidth of each FPGA chip. Our accelerator can achieve two orders of magnitude speedup compared with CPU implementation.

An Accelerating Solution forN-Body MOND Simulation with FPGA-SoC

As a modified-gravity proposal to handle the dark matter problem on galactic scales, Modified Newtonian Dynamics (MOND) has shown a great success. However, theN-body MOND simulation is quite challenged by its computation complexity, which appeals to acceleration of the simulation calculation. In this paper, we present a highly integrated accelerating solution forN-body MOND simulations. By using the FPGA-SoC, which integrates both FPGA and SoC (system on chip) in one chip, our solution exhibits potentials for better performance, higher integration, and lower power consumption. To handle the calculation bottleneck of potential summation, on one hand, we develop a strategy to simplify the pipeline, in which the square calculation task is conducted by the DSP48E1 of Xilinx 7 series FPGAs, so as to reduce the logic resource utilization of each pipeline; on the other hand, advantages of particle-mesh scheme are taken to overcome the bottleneck on bandwidth. Our experiment results show that 2 more pipelines can be integrated in Zynq-7020 FPGA-SoC with the simplified pipeline, and the bandwidth requirement is reduced significantly. Furthermore, our accelerating solution has a full range of advantages over different processors. Compared with GPU, our work is about 10 times better in performance per watt and 50% better in performance per cost.