Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects

Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities such as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them, and test escapes may occur. These undetected faults, associated with weak resistive defects, may affect the FinFET-based SRAM reliability during its lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed allowing the evaluation of the ionizing particle’s impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects can positively or negatively influence the cell reliability against SEUs caused by ionizing particles.

Pseudo-ring tests resolution for dynamic single faults in word-oriented memory

This paper presents single dynamic faults and methods for their detection. Such dynamic faults as dRDF, dDRDF and dIRF are considered in detail. Also, pseudo-ring testing and the principles of single dynamic faults detecting by pseudo-ring tests are considered. The paper presents the resolution determination results for pseudo-ring tests in relation to these faults in the word-oriented memory. Also, a comparative analysis of the pseudo-ring tests with known March tests is done. The results show that pseudo-ring tests with an algorithmic complexity of (30-60)N, where N is the number of all memory cells, can cover from 75 to 100% of all single dynamic faults. This advantage allows using pseudo-ring tests as an alternative to existing classical and March tests.