interconnect impedance
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Interconnect impedance optimization for high speed IO up to 12Gbps under HVM condition

2014 IEEE International Symposium on Electromagnetic Compatibility (EMC) ◽

10.1109/isemc.2014.6899048 ◽

2014 ◽

Cited By ~ 1

Author(s):

Xinjun Zhang ◽

Chunfei Ye ◽

Ming Wei ◽

Weifeng Shu ◽

Xiaoning Ye

Keyword(s):

High Speed ◽

Interconnect Impedance

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Corrections to “Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate” [Jul 09 1047-1060

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2010.2047753 ◽

2010 ◽

Vol 29 (5) ◽

pp. 849-849 ◽

Cited By ~ 2

Author(s):

Navin Srivastava ◽

Chuan Xu ◽

Roberto Suaya ◽

Kaustav Banerjee

Keyword(s):

High Frequency ◽

Conductive Substrate ◽

Impedance Extraction ◽

Interconnect Impedance ◽

Analytical Expressions

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Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2009.2017432 ◽

2009 ◽

Vol 28 (7) ◽

pp. 1047-1060 ◽

Cited By ~ 4

Author(s):

N. Srivastava ◽

R. Suaya ◽

K. Banerjee

Keyword(s):

High Frequency ◽

Conductive Substrate ◽

Impedance Extraction ◽

Interconnect Impedance ◽

Analytical Expressions

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A proposal for accurately modeling frequency-dependent on-chip interconnect impedance

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) ◽

10.1109/isqed.2000.838899 ◽

2002 ◽

Cited By ~ 1

Author(s):

Li-Fu Chang ◽

Keh-Jeng Dhang ◽

C. Bianchi

Keyword(s):

Frequency Dependent ◽

On Chip ◽

Interconnect Impedance

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A system for critical path analysis based on back annotation and distributed interconnect impedance models

Microelectronics Journal ◽

10.1016/s0026-2692(88)80051-x ◽

1988 ◽

Vol 19 (3) ◽

pp. 21-30 ◽

Cited By ~ 21

Author(s):

G.Y. Yacoub ◽

H. Pham ◽

M. Ma ◽

E.G. Friedman

Keyword(s):

Path Analysis ◽

Critical Path ◽

Critical Path Analysis ◽

Interconnect Impedance ◽

Impedance Models

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interconnect impedanceRecently Published Documents

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Interconnect impedance optimization for high speed IO up to 12Gbps under HVM condition

Corrections to “Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate” [Jul 09 1047-1060

Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate

A proposal for accurately modeling frequency-dependent on-chip interconnect impedance

A system for critical path analysis based on back annotation and distributed interconnect impedance models

interconnect impedance
Recently Published Documents