Frequency Domain based Digital Down Conversion Architecture for Software Defined Radio and Cognitive Radio

This paper presents a sampling rate digital down converter that is totally based on frequency domain processing. The proposed DDC is targeted for Software Defined Radio and Cognitive Radio architectures. The proposed architecture is based on replacement of the complex multiplication with direct rotation of the spectrum. Different aspects of frequency domain filtering are also discussed. The Xilinx Virtex-6 family FPGA, XC6VLX240T is used for the implementation and synthesis of the proposed FFT-IFFT based architecture. The overlapping in time domain at the output of the IFFT block is avoided using overlap and add method. In terms area, highly optimized implementation is observed in the proposed architecture when compared to the conventional DDC. The synthesis results have shown that the developed core works at a maximum clock rate of 250 MHz and at the same time occupies only 10% of the slices of FPGA.

A IF Signal Precessing System Design Based on Software Radio Platform

Software radio is a definition of a design thought about how to implement flexible functions by using fixed hardware platform. Any platform based on this is characterized to be universal, standardized, modular, open and highly flexible. Due to some realistic reasons, a software radio platform is hard to be realized. So, most signal processing is operated after mixing. According to software radio requirements, a “FPGA+ADC+DAC” structure is designed. Compared with former processors, this module has broad application prospects with the small size, low power, configurable and programmable feathers. It has multifunction, such as generating IF signals, performing digital down conversion and realizing the synchronous demodulation and the other functions. This module also provides the extended host interface to communicate with upper computers. According to the practical test, take MSK signal for example, if the bit rate is 1Mb/s, bit error rate is lower than 10-6.

Decomposing Numerically Controlled Oscillator in Parallel Digital Down Conversion Architecture

The speed of digital signal processing device restricts the performance of the serial digital down conversion (DDC) architecture when the input of the DDC features a high sampling rate. As a result, the polyphase or parallel structure is adopted to relieve the speed pressure. This paper mainly studies the numerically controlled oscillator (NCO) decomposing in the parallel DDC structure, which can decompose the NCO’s output into several branch signals which then can lower the operating speed of the mixer and the low pass filter (LPF) significantly, making it easier to implement DDC with field programmable gate array (FPGA). The mathematical expressions of the branch NCO outputs applied to the parallel DDC are deduced and the selection principles of the correlated parameters are discussed. The simulation and the experimental results of MATLAB show the corrections of the NCO decomposing technique.