The Algorithm and Structure for Digital Normalized Cross-Correlation by Using First-Order Moment

Normalized cross-correlation is an important mathematical tool in digital signal processing. This paper presents a new algorithm and its systolic structure for digital normalized cross-correlation, based on the statistical characteristic of inner-product. We first introduce a relationship between the inner-product in cross-correlation and a first-order moment. Then digital normalized cross-correlation is transformed into a new calculation formula that mainly includes a first-order moment. Finally, by using a fast algorithm for first-order moment, we can compute the first-order moment in this new formula rapidly, and thus develop a fast algorithm for normalized cross-correlation, which contributes to that arbitrary-length digital normalized cross-correlation being performed by a simple procedure and less multiplications. Furthermore, as the algorithm for the first-order moment can be implemented by systolic structure, we design a systolic array for normalized cross-correlation with a seldom multiplier, in order for its fast hardware implementation. The proposed algorithm and systolic array are also improved for reducing their addition complexity. The comparisons with some algorithms and structures have shown the performance of the proposed method.

Novel Pipelined Scalable Systolic Multiplier Based on Irreducible All-One Polynomials

A planned productive structure issued for the systolic execution of authoritative based limited field duplication over G F(2 m) in light of final 56-bit AOP is proposed in this work. We extricated a recursive increase calculation and utilized it to plan an intermittent and confined piece level reliance outline (DG) for systolic registering. The intermittent piece level DG is changed into a very smal grained DG, and the pipe coating is utilized for snappier mapping into a parallel systolic design. It doesn't require any overall correspondences for measured decline, in contrast to most current developments. The suggested bit-parallel systolic structure is similar to the parallel systolic structure, however the quantity of registers is altogether lower.

Nanoarrays for Systolic Biosequence Analysis

Applications like biosequence alignment are currently addressed using traditional technology at the price of a huge overhead in terms of area and power dissipation. Nanoarrays are expected to outperform current limits especially in terms of processing capabilities. The purpose of this work is to assess the real terms of these expectations. Our contribution deals with: (i) a new model for nanowire FETs used to evaluate transistor’s essential performance; (ii) a new switch-level simulator for nanoarray structure used to evaluate its switching activity; (iii) a nanoarray implementation for biosequence alignment based on a systolic array and the modeling of its essential performance based on (i) and (ii); (iv) the evaluation of the potential improvement of the nanoarray-based systolic structure with respect to an equivalent CMOS one in terms of processing capabilities, area, and power dissipation. Depending on the possible technological scenario, the performance of nanoarray is impressive, especially considering the density achievable in terms of processing per unit area. A wide solution space can be explored to find the optimal solution in terms of trading power and performance considering the technological limitations of a realistic implementation.

A Design of VB-DDC Using DA-Based Systolic FIR Filter

In this paper, we present yet another design of the variable-bandwidth digital down-converter (VB-DDC). The shaping filter in the DDC architecture is substitute with a method which is implemented with fully pipelined computing structure of systolic decomposition for distributed arithmetic (DA) based FIR filer. The systolic structure of the FIR filter involves significantly less memory and complexity compared with the existing ones. The effectiveness of the design is validated by the proposed FPGA implementation results.

SYSTOLIC MERGING AND RANKING OF VOTES FOR THE GENERALIZED HOUGH TRANSFORM

In this paper we present and analyze a systolic structure to support the Generalized Hough Transform. Among the structural methods for object recognition, this transform is well established for its flexibility and noise immunity. Its use in actual systems has been however limited by the computational cost associated with the management of votes. Previous work has shown that a limited amount of memory can substitute the large address space required for building the histogram of votes. The systolic queue here introduced substitutes the address space required in a M- dimensional voting process, where the quantization of each dimension into Q bins yields a space complexity O(QM). An N-stage queue uses 3 M log(Q) memory bits at each stage and is capable of accumulating the incoming votes on the fly. The flow of data within the queue is designed to minimize the probability that new votes are lost because of overflow. We derive analytic expressions for the growth of the queue during the set-up period and for the time each new vote spends within the queue if it is not accumulated; furthermore, we show the conditions for the arrival times of a couple of coincident addresses to be detected and merged. The analysis of the time behaviour of the queue supports the experimental evidence that such a structure performs the accumulating process very reliably. A VLSI integrated circuit embedding a 50-stage queue is the third in a chip-set for the real time implementation of the Generalized Hough Transform.