hierarchical verification
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Author(s):  
Carna Zivkovic ◽  
Christoph Grimm ◽  
Markus Olbrich ◽  
Oliver Scharf ◽  
Erich Barke

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 16795-16815 ◽  
Author(s):  
C. Dechsupa ◽  
W. Vatanawood ◽  
A. Thongtak

Author(s):  
Sidi Mohamed Beillahi ◽  
Mohamed Yousri Mahmoud ◽  
Sofiène Tahar

2014 ◽  
Vol 670-671 ◽  
pp. 1441-1446
Author(s):  
Jing Wang ◽  
Fei Wang

An advanced verification platfrom based on UVM architecture is implemented in this paper. This paper presents a hierarchical verification environment that is portable, reusable, and easy to extend, which is constructed based on an object oriented language named System Verilog. The verification platform is applied to verify a RFID (Radio Frequency Identification) tag chip which is compliant with the ISO/IEC15693 standard, communicates with a reader outside through a RF analog circuitry, completes anti-collision flow, selects card, authenticates based on SM7 algorithm and controls the writing and reading of EEPROM inside. According to the instruction supported by the tag chip is wide and variety, and further more it’s very rich in the command frame contents, the advanced verification platform which achieves the constraint-random stimulus generation, functional coverage and self-check mechanism, reduces the verification cycle, improves verification efficiency and ensures verification adequacy.


2008 ◽  
Vol 24 (1-3) ◽  
pp. 117-128 ◽  
Author(s):  
Joonhyuk Yoo ◽  
Manoj Franklin

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