performance scaling
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Author(s):  
Matthew Leighton ◽  
David Sivak

Abstract Motor-driven intracellular transport of organelles, vesicles, and other molecular cargo is a highly collective process. An individual cargo is often pulled by a team of transport motors, with numbers ranging from only a few to several hundred. We explore the behavior of these systems using a stochastic model for transport of molecular cargo by an arbitrary number N of motors, finding analytic solutions for the N-dependence of the velocity, precision of forward progress, energy flows between different system components, and efficiency. In two opposing regimes, we show that these properties obey simple scaling laws with N. Finally, we explore trade-offs between performance metrics as N is varied, providing insight into how different numbers of motors might be well-matched to distinct contexts where different performance metrics are prioritized.


2021 ◽  
Author(s):  
Sage Hahn ◽  
Max M Owens ◽  
DeKang Yuan ◽  
Anthony C Juliano ◽  
Alexandra Potter ◽  
...  

The use of pre-defined parcellations on surface-based representations of the brain as a method for data reduction is common across neuroimaging studies. In particular, prediction-based studies typically employ parcellation-driven summaries of brain measures as input to predictive algorithms, but the choice of parcellation and its influence on performance is often ignored. Here we employed pre-processed structural magnetic resonance imaging data (sMRI) from the ABCD Study to examine the relationship between 220 parcellations and out-of-sample predictive performance across 45 phenotypic measures in a large sample of 9-10-year-old children (N=9,432). Choice of Machine Learning (ML) pipeline and use of alternative multiple parcellation-based strategies were also assessed. Relative parcellation performance was dependent on the spatial resolution of the parcellation, with larger numbers of parcels (up to ~4000) outperforming coarser parcellations, according to a power-law scaling of between 1/4 and 1/3. Performance was further influenced by the type of parcellation, ML pipeline, and general strategy, with existing literature-based parcellations, a support vector based pipeline, and ensembling across multiple parcellations, respectively, as the highest performing. These findings highlight the choice of parcellation as an important influence on downstream predictive performance, showing in some cases that switching to a higher resolution parcellation can yield a relatively large boost to performance.


2021 ◽  
Author(s):  
Wei Lou ◽  
Lei Xun ◽  
Amin Sabet ◽  
Jia Bi ◽  
Jonathon Hare ◽  
...  

2020 ◽  
Vol 125 (15) ◽  
Author(s):  
M. R. Gomez ◽  
S. A. Slutz ◽  
C. A. Jennings ◽  
D. J. Ampleford ◽  
M. R. Weis ◽  
...  

2020 ◽  
Vol 28 (9) ◽  
pp. 12755 ◽  
Author(s):  
Léonard M. Krüger ◽  
Aline S. Mayer ◽  
Yoshitomo Okawachi ◽  
Xingchen Ji ◽  
Alexander Klenner ◽  
...  

2020 ◽  
Vol 168 ◽  
pp. 115157 ◽  
Author(s):  
Pengjia Dou ◽  
Shuwei Zhao ◽  
Shanshan Xu ◽  
Xue-Mei Li ◽  
Tao He

2019 ◽  
Vol 8 (3) ◽  
pp. 1055-1062

Manufacturing fault-free System on Chips (SoCs) with performance scaling is a challenging task. The Network on Chip (NoC) architecture offers scalability and reliability to the SoC designs. In this paper, the fault detection and correction mechanism for a congestion-free Router architecture along with Mesh-NoC for different sizes are discussed. The proposed hardware architecture of NoC-Router includes Input registers (which store five -port inputs with Fault injection), Error Correction Code (that encodes the input data) followed by packet formation with Arbitration mechanism (that grants the permission to priority based encoder). The prior packet data is input to the adaptive-XY routing and it operates with the various congestion issues on choosing the shortest route. The detection and correction of the faulty bits from the network are monitored by ECC decoder. This NoC router can tolerate transient fault; provides low-latency and high throughput performance for all MPSoC applications. The Normal –XY Routing algorithm is incorporated in same router for comparison purpose. The synthesis results includes chip area, and maximum operating frequency over Artix-7 FPGA technology. Outcomes are tabulated and they show a marked improvement over previous cases. The performance evaluation is considered in terms of average latency and maximum throughput at different input traffic. It’s analyzed for novelty features as well.


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